公开(公告)号：US20240062813A1

公开(公告)日：2024-02-22

申请号：US18385281

申请日：2023-10-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran

IPC: G11C11/54 ,  G06N3/063 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C11/54 ,  G06N3/063 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H10B41/30

Abstract: A first example comprises programming a memory cell to store a value; applying a series of currents of increasing size to a bit line of the memory cell; and measuring a voltage of a control gate terminal of the memory cell to determine a bias. A second example comprises programming a memory cell to store a value; applying a predetermined current to a bit line of the memory cell; and measuring a voltage of a control gate terminal of the memory cell to determine a bias.

公开(公告)号：US20240062812A1

公开(公告)日：2024-02-22

申请号：US18385256

申请日：2023-10-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran

IPC: G11C11/54 ,  G06N3/063 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C11/54 ,  G06N3/063 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H10B41/30

Abstract: In one example, a method comprises programming a memory cell capable of storing any of N values with 1 of the N values; applying a series of currents of increasing size to a bit line of the memory cell; comparing a voltage of the bit line to a reference voltage to generate a comparison output; and when the comparison output changes value, measuring a voltage of a control gate terminal of the memory cell and storing the voltage in a bias lookup table.

公开(公告)号：US11847556B2

公开(公告)日：2023-12-19

申请号：US17875281

申请日：2022-07-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G06N3/065 ,  G11C11/54 ,  G06F1/03 ,  G06F17/16 ,  G11C11/56 ,  G06F11/16 ,  G11C13/00 ,  G11C29/44 ,  G06F7/78

CPC classification number: G06N3/065 ,  G06F1/03 ,  G06F7/78 ,  G06F11/1666 ,  G06F17/16 ,  G11C11/54 ,  G11C11/5635 ,  G11C13/0021 ,  G11C29/44

Abstract: Numerous examples of a precision programming apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. In one example, a neuron output circuit for providing a current to program as a weight value in a selected memory cell in a vector-by-matrix multiplication array is disclosed, the neuron output circuit comprising a first adjustable current source to generate a scaled current in response to a neuron current to implement a positive weight, and a second adjustable current source to generate a scaled current in response to a neuron current to implement a negative weight.

公开(公告)号：US11798644B2

公开(公告)日：2023-10-24

申请号：US17669793

申请日：2022-02-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiaozhou Qian ,  Yaohua Zhu

IPC: G11C7/00 ,  G11C29/04 ,  G11C8/10

CPC classification number: G11C29/04 ,  G11C8/10

Abstract: Various embodiments are disclosed for performing address fault detection in a memory system using a hierarchical ROM encoding system. In one embodiment, a hierarchical ROM encoding system comprises two levels of ROM encoders that are used to detect an address fault. In another embodiment, a hierarchical ROM encoding system comprises three levels of ROM encoders that are used to detect an address fault.

公开(公告)号：US11797834B2

公开(公告)日：2023-10-24

申请号：US17885431

申请日：2022-08-10

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G06N3/065 ,  G11C11/56 ,  G06F3/06 ,  G06F17/16 ,  G06N3/08 ,  G11C13/00 ,  G11C16/04 ,  G11C16/28 ,  G06N3/048

CPC classification number: G06N3/065 ,  G06F3/061 ,  G06F3/0688 ,  G06F17/16 ,  G06N3/048 ,  G06N3/08 ,  G11C11/5642 ,  G11C13/004 ,  G11C16/0425 ,  G11C16/28 ,  G11C2211/563 ,  G11C2213/15

Abstract: Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network. In one embodiment, a method comprises receiving a first voltage, multiplying the first voltage by a coefficient to generate a second voltage, applying the first voltage to a gate of one of a reference transistor and a selected memory cell, applying the second voltage to a gate of the other of a reference transistor and a selected memory cell, and using the reference transistor in a sense operation to determine a value stored in the selected memory cell.

公开(公告)号：US11769558B2

公开(公告)日：2023-09-26

申请号：US17482095

申请日：2021-09-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Viktor Markov ,  Alexander Kotov

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14

CPC classification number: G11C16/3427 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C2216/04

Abstract: A method of programing a memory device having a plurality of memory cell groups where each of the memory cell group includes N non-volatile memory cells, where N is an integer greater than or equal to 2. For each memory cell group, the method includes programming each of the non-volatile memory cells in the memory cell group to a particular program state, performing multiple read operations on each of the non-volatile memory cells in the memory cell group, identifying one of the non-volatile memory cells in the memory cell group that exhibits a lowest read variance during the multiple read operations, deeply programming all of the non-volatile memory cells in the memory cell group except the identified non-volatile memory cell, and programming the identified non-volatile memory cell in the memory cell group with user data.

公开(公告)号：US11729970B2

公开(公告)日：2023-08-15

申请号：US17121555

申请日：2020-12-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: H01L27/11531 ,  G06N3/08 ,  G11C16/04 ,  H01L29/788 ,  H10B41/42

CPC classification number: H10B41/42 ,  G06N3/08 ,  G11C16/0425 ,  H01L29/7883

Abstract: Numerous embodiments for reading a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input pulses applied to a terminal of the selected memory cell, further resulting in a series of output signals that are summed to determine the value stored in the selected memory cell. In another embodiment, an input comprises a set of input bits, where each input bit results in a single pulse or no pulse being applied to a terminal of the selected memory cell, further resulting in a series of output signals which are then weighted according to the binary bit location of the input bit, and where the weighted signals are then summed to determine the value stored in the selected memory cell.

公开(公告)号：US20230252265A1

公开(公告)日：2023-08-10

申请号：US18126233

申请日：2023-03-24

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Farnood Merrikh Bayat ,  Xinjie Guo ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten

IPC: G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C16/34 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/06

CPC classification number: G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C16/3436 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688

Abstract: A method of scanning N×N pixels using a vector-by-matrix multiplication array by (a) associating a filter of M×M pixels adjacent first vertical and horizontal edges, (b) providing values for the pixels associated with different respective rows of the filter to input lines of different respective N input line groups, (c) shifting the filter horizontally by X pixels, (d) providing values for the pixels associated with different respective rows of the horizontally shifted filter to input lines, of different respective N input line groups, which are shifted by X input lines, (e) repeating steps (c) and (d) until a second vertical edge is reached, (f) shifting the filter horizontally to be adjacent the first vertical edge, and shifting the filter vertically by X pixels, (g) repeating steps (b) through (e) for the vertically shifted filter, and (h) repeating steps (f) and (g) until a second horizontal edge is reached.

公开(公告)号：US20230238453A1

公开(公告)日：2023-07-27

申请号：US18126954

申请日：2023-03-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  XIAN LIU ,  CHIEN-SHENG SU ,  Nhan DO ,  CHUNMING WANG

IPC: H01L29/66 ,  H01L29/788 ,  H01L27/07 ,  H01L29/08 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/66825 ,  H01L29/788 ,  H01L27/0705 ,  H01L29/0847 ,  H01L29/40114 ,  H01L28/00 ,  H01L29/42328 ,  H01L29/66545 ,  G11C2216/10 ,  H01L29/6653

Abstract: A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

公开(公告)号：US20230223077A1

公开(公告)日：2023-07-13

申请号：US18124334

申请日：2023-03-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C11/54 ,  H01L29/423 ,  G11C16/14 ,  H01L29/788 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C11/54 ,  H01L29/42324 ,  G11C16/14 ,  H01L29/7883 ,  H01L29/42328 ,  G11C16/10 ,  G06N3/045 ,  H10B41/30 ,  G11C16/0483

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.