公开(公告)号：US08546818B2

公开(公告)日：2013-10-01

申请号：US13401446

申请日：2012-02-21

Applicant: Wen-Huang Liu ,  Chen-Fu Chu ,  Jiunn-Yi Chu ,  Chao-Chen Cheng ,  Hao-Chun Cheng ,  Feng-Hsu Fan ,  Yuan-Hsiao Chang

Inventor： Wen-Huang Liu ,  Chen-Fu Chu ,  Jiunn-Yi Chu ,  Chao-Chen Cheng ,  Hao-Chun Cheng ,  Feng-Hsu Fan ,  Yuan-Hsiao Chang

IPC: H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/109 ,  H01L27/15 ,  H01L29/26 ,  H01L31/12 ,  H01L29/22 ,  H01L31/072 ,  H01L33/00

CPC classification number: H01L33/14 ,  H01L27/15 ,  H01L33/38 ,  H01L33/385 ,  H01L33/40 ,  H01L33/44 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Techniques for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current-guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a substrate) may be provided. For some embodiments, both a current-guiding structure and second current path may be provided.

Abstract translation: 提供了用于控制诸如LED的半导体器件中的电流的技术。 对于一些实施例，可以提供电流引导结构，包括相邻的高和低接触区域。 对于一些实施例，可以提供第二电流路径（除了n接触焊盘和衬底之间的电流路径之外）。 对于一些实施例，可以提供电流引导结构和第二电流路径。

公开(公告)号：US08519444B2

公开(公告)日：2013-08-27

申请号：US12879447

申请日：2010-09-10

Applicant: Annie Lum ,  Derek C. Tao ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Vineet Kumar Agrawal ,  Keun-Young Kim ,  Pyong Yun Cho

Inventor： Annie Lum ,  Derek C. Tao ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Vineet Kumar Agrawal ,  Keun-Young Kim ,  Pyong Yun Cho

IPC: H01L27/118

CPC classification number: G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L27/0207 ,  H01L27/088 ,  Y02P90/265

Abstract: The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.

Abstract translation: 上述布局，装置结构和方法利用虚设装置将边缘结构和/或非允许结构的扩散区域扩展到虚设装置。 这种扩散区域的扩展可解决或减少LOD和边缘效应问题。 此外，在边缘装置旁边处理伪装置的栅极结构也仅允许在虚设装置旁边添加一个虚拟结构，并将该不动产保存在半导体芯片上。 虚拟设备被禁用，其性能不重要。 因此，利用虚设装置根据设计规则扩展边缘结构和/或非允许结构的扩散区域允许分辨率或降低或LOD和边缘效应发生，而不会降低成品率或增加布局面积。

公开(公告)号：US08482990B2

公开(公告)日：2013-07-09

申请号：US13025872

申请日：2011-02-11

Applicant: Hong-Chen Cheng ,  Ming-Yi Lee ,  Kuo-Hua Pan ,  Jung-Hsuan Chen ,  Li-Chun Tien ,  Cheng Hung Lee ,  Hung-Jen Liao

Inventor： Hong-Chen Cheng ,  Ming-Yi Lee ,  Kuo-Hua Pan ,  Jung-Hsuan Chen ,  Li-Chun Tien ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC: G11C7/10

CPC classification number: G11C5/06 ,  G11C5/147 ,  G11C5/148 ,  G11C11/417

Abstract: A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.

Abstract translation: 电路包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，第三NMOS晶体管和第四NMOS晶体管。 PMOS晶体管和NMOS晶体管被配置为提供具有第一参考电压的第一电压参考节点和具有第二参考电压的第二参考电压节点。 第一参考电压和第二参考电压分别用作存储器单元的第一参考电压和第二参考电压。

公开(公告)号：USD685334S1

公开(公告)日：2013-07-02

申请号：US29419098

申请日：2012-04-25

Applicant: Chen-Fu Chu ,  Chao-Chen Cheng

Designer： Chen-Fu Chu ,  Chao-Chen Cheng

公开(公告)号：US08466479B2

公开(公告)日：2013-06-18

申请号：US12986946

申请日：2011-01-07

Applicant: Chen-Fu Chu ,  Hao-Chun Cheng ,  Feng-Hsu Fan ,  Wen-Huang Liu ,  Chao-Chen Cheng

Inventor： Chen-Fu Chu ,  Hao-Chun Cheng ,  Feng-Hsu Fan ,  Wen-Huang Liu ,  Chao-Chen Cheng

IPC: H01L33/00 ,  H01L21/00

CPC classification number: H01L33/20 ,  H01L33/0095 ,  H01L33/08 ,  H01L33/22

Abstract: Systems and methods are disclosed for fabricating a semiconductor light-emitting diode (LED) device by forming an n-doped gallium nitride (n-GaN) layer on the LED device and roughening the surface of the n-GaN layer to extract light from an interior of the LED device.

Abstract translation: 公开了用于通过在LED器件上形成n掺杂氮化镓（n-GaN）层并使n-GaN层的表面粗糙化从而提取出来的光的系统和方法来制造半导体发光二极管（LED）器件 LED装置的内部。

公开(公告)号：US08457257B2

公开(公告)日：2013-06-04

申请号：US12119902

申请日：2008-05-13

Applicant: Fang-Chen Cheng ,  Lei Song

Inventor： Fang-Chen Cheng ,  Lei Song

IPC: H03D1/00

CPC classification number: H04L27/2647 ,  H04L5/0007 ,  H04L5/0053 ,  H04L23/02

Abstract: The present invention provides a method for implementation in a random access channel receiver. One embodiment of the method includes generating at least one frequency domain reference sequence by multiplying a generator function and a first frequency domain root CAZAC sequence. The frequency domain reference sequence(s) is generated in response to receiving a signal at the random access channel receiver. This embodiment of the method also includes correlating the received signal and the frequency domain reference sequence(s).

Abstract translation: 本发明提供了一种在随机接入信道接收机中实现的方法。 该方法的一个实施例包括通过将生成函数和第一频域根CAZAC序列相乘来生成至少一个频域参考序列。 响应于在随机接入信道接收机处接收到信号而产生频域参考序列。 该方法的该实施例还包括将接收信号和频域参考序列相关联。

公开(公告)号：US20130134563A1

公开(公告)日：2013-05-30

申请号：US13308249

申请日：2011-11-30

Applicant: Yao-Chun Chuang ,  Chang-Chia Huang ,  Tsung-Shu Lin ,  Chen-Cheng Kuo ,  Chen-Shien Chen

Inventor： Yao-Chun Chuang ,  Chang-Chia Huang ,  Tsung-Shu Lin ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC: H01L23/58 ,  H01L21/28 ,  H01L23/48

CPC classification number: H01L24/11 ,  H01L23/293 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05022 ,  H01L2224/05086 ,  H01L2224/05091 ,  H01L2224/05124 ,  H01L2224/05541 ,  H01L2224/05572 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less than the dimension of the top metal connector. The dimension of the top metal connector is less than the dimensions of an opening in the second passivation layer and an opening in the polymer layer.

Abstract translation: 结构包括形成在接合焊盘下方的顶部金属连接器。 接合焊盘由第一钝化层和第二钝化层包围。 聚合物层进一步形成在第二钝化层上。 第一钝化层中的开口的尺寸小于顶部金属连接器的尺寸。 顶部金属连接器的尺寸小于第二钝化层中的开口的尺寸和聚合物层中的开口的尺寸。

公开(公告)号：US20130128655A1

公开(公告)日：2013-05-23

申请号：US13303231

申请日：2011-11-23

Applicant: Hong-Chen CHENG ,  Chia-En HUANG ,  Chih-Chieh CHIU ,  Jung-Ping YANG

Inventor： Hong-Chen CHENG ,  Chia-En HUANG ,  Chih-Chieh CHIU ,  Jung-Ping YANG

IPC: G11C11/34 ,  H03L5/00

CPC classification number: G11C8/10 ,  G11C11/413 ,  G11C11/418

Abstract: An apparatus includes a level shifter and a switching circuit. The level shifter includes an input, a first output, and second output having a logic value complementary to a logic value of the first output. The switching circuit includes a data input, a feedback input coupled to the second output of the level shifter, and an output coupled to the input of the level shifter. The switching circuit is configured to selectively latch, based on a select signal, a logic state of the level shifter at the second output.

Abstract translation: 一种装置包括电平移位器和开关电路。 电平移位器包括具有与第一输出的逻辑值互补的逻辑值的输入，第一输出和第二输出。 切换电路包括数据输入，耦合到电平移位器的第二输出的反馈输入以及耦合到电平移位器的输入的输出。 开关电路被配置为基于选择信号选择性地锁存第二输出处的电平移位器的逻辑状态。

公开(公告)号：US20130093079A1

公开(公告)日：2013-04-18

申请号：US13276090

申请日：2011-10-18

Applicant: Shang-Yun Tu ,  Yao-Chun Chuang ,  Ming Hung Tseng ,  Chen-Cheng Kuo ,  Chen-Shien Chen

Inventor： Shang-Yun Tu ,  Yao-Chun Chuang ,  Ming Hung Tseng ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC: H01L23/498

CPC classification number: H01L24/16 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/061 ,  H01L2224/06132 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13541 ,  H01L2224/1405 ,  H01L2224/141 ,  H01L2224/16105 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/206 ,  H01L2224/05552

Abstract: A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.

公开(公告)号：US20130093075A1

公开(公告)日：2013-04-18

申请号：US13271766

申请日：2011-10-12

Applicant: Hao-Juin Liu ,  Chita Chuang ,  Chen-Cheng Kuo ,  Chen-Shien Chen

Inventor： Hao-Juin Liu ,  Chita Chuang ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC: H01L23/34 ,  H01L21/58

CPC classification number: H01L23/3114 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83385 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/27 ,  H01L2924/0665 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: An embodiment is a structure. The structure comprises a substrate, a chip, and a reinforcement component. The substrate has a first surface, and the first surface comprises depressions. The chip is over and attached to the first surface of the substrate. The reinforcement component is over a first area of the first surface of the substrate. The first area is not under the chip. The reinforcement component has a portion disposed in at least some of the depressions in the first area.

Abstract translation: 一个实施例是一种结构。 该结构包括基底，芯片和增强部件。 衬底具有第一表面，并且第一表面包括凹陷。 芯片结束并附着到基板的第一表面。 加强部件在基板的第一表面的第一区域之上。 第一个区域不在芯片之下。 加强部件具有设置在第一区域中的至少一些凹部中的部分。