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公开(公告)号：US08640072B1
公开(公告)日：2014-01-28
申请号：US13562538
申请日：2012-07-31
IPC分类号： G06F17/50 , H01L21/4763 , H01L29/40
CPC分类号： H01L21/76877 , G06F17/5077 , H01L21/4763 , H01L21/76816 , H01L23/5226 , H01L29/401 , H01L2924/0002 , H01L2924/00
摘要： A method includes forming a connection between a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A via location for a first via between the first metal layer and the second metal layer is identified. Additional locations for first additional vias are determined. The first additional vias are determined to be necessary for stress migration issues. Additional locations necessary for second additional vias are determined. The second additional vias are determined to be necessary for electromigration issues. The first via and the one of the group consisting of (i) the first additional vias and second additional vias (ii) the first additional vias plus a number of vias sufficient for electromigration issues taking into account that the first additional vias, after taking into account the stress migration issues, still have an effective via number greater than zero.
摘要翻译： 一种方法包括在第一金属层和第二金属层之间形成连接。 第二金属层在第一金属层之上。 识别用于第一金属层和第二金属层之间的第一通孔的通孔位置。 确定第一个额外通孔的附加位置。 第一个额外的通孔被确定为压力迁移问题所必需的。 确定第二个额外通孔所需的附加位置。 第二个额外的通孔被确定为电迁移问题所必需的。 第一个通路和一个组（i）第一个额外的通孔和第二个额外的通孔（ii）第一个额外的通孔加上一些足够电迁移问题的通孔，考虑到第一个额外的通孔， 考虑到压力迁移问题，仍然有效通过数字大于零。
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32.发明申请TECHNIQUES FOR CHECKING COMPUTER-AIDED DESIGN LAYERS OF A DEVICE TO REDUCE THE OCCURRENCE OF MISSING DECK RULES 有权检查设备的计算机辅助设计层的技术，以减少错误的规则规则的发生公开(公告)号：US20130326446A1
公开(公告)日：2013-12-05
申请号：US13484022
申请日：2012-05-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A technique for computer-aided design layer checking of an integrated circuit design includes generating a representation of a device (e.g., a parameterized cell). Computer-aided design (CAD) layers are sequentially removed from the parameterized cell and a determination is made as to whether expected errors are detected or missed by an associated deck. The associated deck is then modified to detect the expected errors that are missed.
摘要翻译： 用于集成电路设计的计算机辅助设计层检查的技术包括生成设备（例如，参数化单元）的表示。 计算机辅助设计（CAD）层从参数化的单元中顺序地移除，并且确定是否由相关联的卡座检测到或错过预期的错误。 然后修改相关甲板以检测错过的预期错误。
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公开(公告)号：US20130105986A1
公开(公告)日：2013-05-02
申请号：US13285073
申请日：2011-10-31
CPC分类号： G06F13/4027 , G06F17/5077 , H01L23/5221 , H01L23/528 , H01L23/5283 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises conductive buses and conductive bridges. A respective conductive bridge is conductively coupled to at least two portions of at least one of the conductive buses. At least N plus one (N+1) vias are coupled between every one of the conductive bridges and a respective feature in an integrated circuit when: (1) a width of the respective conductive bridge is less than a width of each of the at least two portions of the at least one of the conductive buses to which the respective conductive bridge is coupled, and (2) a distance along the respective conductive bridge and at least one of the vias is less than a critical distance. N is a number of conductive couplings between the respective one of the conductive bridges and the at least one of the conductive buses.
摘要翻译： 半导体器件包括导电总线和导电桥。 相应的导电桥与至少一个导电总线的至少两个部分导电耦合。 当以下情况下，至少N + 1个（N + 1）通孔耦合在每个导电桥和集成电路中的相应特征之间：（1）相应导电桥的宽度小于每个导体桥的宽度 所述至少一个导电总线的至少一个导体总线的至少两个部分相互连接，并且（2）沿相应导电桥和至少一个通孔的距离小于临界距离。 N是在相应的一个导电桥和至少一个导电总线之间的多个导电耦合。
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34.发明授权Low temperature, high quality silicon dioxide thin films deposited using tetramethylsilane (TMS) for stress control and coverage applications 有权使用四甲基硅烷（TMS）沉积的低温，高品质二氧化硅薄膜用于应力控制和覆盖应用公开(公告)号：US06531193B2
公开(公告)日：2003-03-11
申请号：US09734232
申请日：2000-12-11
申请人： Stephen J. Fonash , Xin Lin , Douglas M. Reber
发明人： Stephen J. Fonash , Xin Lin , Douglas M. Reber
IPC分类号： C23C1640
CPC分类号： H01L21/02164 , C23C16/402 , C23C16/5096 , H01L21/02211 , H01L21/02274 , H01L21/02337 , H01L21/31612
摘要： Silicon dioxide thin film have been deposited at temperatures from 25° C. to 250° C. by plasma enhanced chemical vapor deposition (PECVD) using tetramethylsilane (TMS) as the silicon containing precursor. At these temperatures, the PETMS oxide films have been found to exhibit adjustable stress and adjustable conformality. Post deposition annealing in forming gas at or below the deposition temperatures has been shown to be very effective in improving the PETMS oxide properties while preserving the low temperature aspect of the PETMS oxides.
摘要翻译： 通过使用四甲基硅烷（TMS）作为含硅前体的等离子体增强化学气相沉积（PECVD），在25℃至250℃的温度下沉积二氧化硅薄膜。 在这些温度下，已经发现PETMS氧化物膜具有可调节的应力和可调整的共形性。 已经表明，在沉积温度或低于沉积温度的成形气体中的后沉积退火在改善PETMS氧化物性能同时保持PETMS氧化物的低温方面是非常有效的。
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35.发明授权Low temperature, high quality silicon dioxide thin films deposited using tetramethylsilane (TMS) 失效使用四甲基硅烷（TMS）沉积的低温，高品质二氧化硅薄膜
公开(公告)号：US6159559A
公开(公告)日：2000-12-12
申请号：US110923
申请日：1998-07-06
IPC分类号： C23C16/40 , C23C16/509 , H01L21/316
CPC分类号： H01L21/02126 , C23C16/402 , C23C16/5096 , H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/02315 , H01L21/02337 , H01L21/31612
摘要： Silicon dioxide thin films have been deposited at temperatures from 40.degree. C. to 250.degree. C. by plasma enhanced chemical vapor deposition (PECVD) using tetramethylsilane (TMS) as the silicon containing precursor. The properties of the PECVD TMS oxides (PETMS-Oxs) were analyzed with Fourier TransformInfrared (FTIR) transmissionspectroscopy, BOEand P-etch rates and both current-voltage (I-V) and capacitance-voltage (C-V) electrical characterization. It was found that the deposition rate for films produced from TMS increased with decreasing temperature; that the --OH inclusions could be affected by TMS flow rate; and that He dilution rate affected trapping for films produced over the temperature range explored. At both 130.degree. C. and 250.degree. C., deposition conditions were identified which formed high quality as-deposited oxide films. Under the best conditions, unannealed Al/PETMS-Ox/c-Si capacitor structures displayed flat band voltages of V.sub.fb -2.9 V and breakdown fields (V.sub.bd) in excess of 8 MV/cm. These PETMS-Ox films also show low leakage current densities
摘要翻译： 通过使用四甲基硅烷（TMS）作为含硅前体的等离子体增强化学气相沉积（PECVD），在40℃至250℃的温度下沉积二氧化硅薄膜。 使用傅里叶变换红外（FTIR）透射光谱，BOE和P蚀刻速率以及电流 - 电压（I-V）和电容电压（C-V）电特征来分析PECVD TMS氧化物（PETMS-Oxs）的性质。 发现由TMS产生的薄膜的沉积速率随着温度的降低而增加; -OH夹杂物可能受TMS流速的影响; 并且他的稀释率影响了在所探索的温度范围内产生的膜的捕获。 在130℃和250℃下，确定沉积条件，形成高质量的沉积氧化膜。 在最佳条件下，未退火的Al / PETMS-Ox / c-Si电容器结构显示Vfb -2.9V的平坦带电压和超过8MV / cm的击穿场（Vbd）。 这些PETMS-Ox膜也显示出低于10-9A / cm 2的低泄漏电流密度，其可以保持在超过4.5MV / cm的场。 PETMS氧化物电气质量和工艺简单性相结合，为低温，大面积应用提供了有吸引力的氧化物沉积技术。
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公开(公告)号：US5491871A
公开(公告)日：1996-02-20
申请号：US163018
申请日：1993-12-08
CPC分类号： H05K3/1233 , H05K2203/082 , H05K2203/085 , H05K3/26
摘要： A solder paste or conductive ink printer stencil wiper apparatus combining a dual action of sucking stencil holes and simultaneously wiping the bottom of the stencil for excess solder. The apparatus includes a vacuum nozzle constructed and arranged to draw excess solder gathered in the holes of the stencil through the nozzle to a collection reservoir. The apparatus also includes a wiping element for wiping the bottom of the stencil at the same time the vacuum is sucking solder out of the stencil holes. The wiper includes a wiper fabric to wipe the bottom of the stencil. The fabric is provided on a roll, and the fabric is pulled through a series of rollers by a motor and collected on a take-up roller.
摘要翻译： 焊膏或导电油墨打印机模板擦拭器装置组合吸取模板孔的双重动作，同时擦拭模板的底部以用于多余的焊料。 该设备包括一个真空喷嘴，该真空喷嘴被构造和布置成将聚集在模板孔中的多余的焊料通过喷嘴吸入收集容器。 该设备还包括用于在模板孔的真空吸附焊料的同时擦拭模板的底部的擦拭元件。 擦拭器包括用于擦拭模板底部的擦拭织物。 织物设置在卷筒上，织物通过马达被牵引通过一系列的辊子并收集在卷取辊上。
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37.发明授权Semiconductor package with embedded capacitor and methods of manufacturing same 有权具有嵌入式电容器的半导体封装及其制造方法相同公开(公告)号：US09548266B2
公开(公告)日：2017-01-17
申请号：US14469645
申请日：2014-08-27
IPC分类号： H01L23/522 , H01L49/02
CPC分类号： H01L28/60 , H01L23/3114 , H01L23/4824 , H01L23/485 , H01L23/5223 , H01L24/02 , H01L24/12 , H01L24/13 , H01L2224/02331 , H01L2224/02379 , H01L2224/04105 , H01L2224/12105 , H01L2224/13024 , H01L2224/24137 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.
摘要翻译： 描述了具有嵌入式电容器的半导体封装和相应的制造方法。 具有嵌入式电容器的半导体封装包括半导体管芯，该半导体管芯具有延伸穿过半导体管芯的第一侧的至少一部分的第一金属层和形成在半导体管芯的第一侧上的封装结构。 嵌入式电容器的第一电导体形成在半导体管芯的第一金属层中。 封装结构包括在其中形成有嵌入式电容器的第二电导体的第二金属层。 嵌入式电容器的电介质位于半导体管芯或半导体封装的封装结构内，以使第一电导体与嵌入式电容器的第二电导体隔离。
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公开(公告)号：US09443804B2
公开(公告)日：2016-09-13
申请号：US13956068
申请日：2013-07-31
IPC分类号： H01L23/48 , H01L23/532 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/768 , H01L21/76846 , H01L21/76849 , H01L23/528 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate, a dielectric layer supported by the substrate, an interconnect adjacent the dielectric layer, the interconnect including a conduction material and a barrier material disposed along sidewalls of the interconnect between the conduction material and the dielectric layer, and a layer disposed over the interconnect to establish an interface between the conduction material, the barrier material, and the layer. A plate is disposed along a section of the interconnect to interrupt the interface.
摘要翻译： 半导体器件包括衬底，由衬底支撑的电介质层，与电介质层相邻的互连，所述互连包括传导材料和沿导电材料和电介质层之间的互连侧壁设置的阻挡材料，以及层 布置在互连上以建立导电材料，阻挡材料和层之间的界面。 沿着互连的一部分布置板以中断接口。
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公开(公告)号：US20160064294A1
公开(公告)日：2016-03-03
申请号：US14470383
申请日：2014-08-27
CPC分类号： H01L21/4846 , H01L22/34 , H01L23/522 , H01L23/562 , H01L23/585 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/81 , H01L24/85 , H01L24/92 , H01L24/94 , H01L2224/02311 , H01L2224/0237 , H01L2224/02371 , H01L2224/0239 , H01L2224/039 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05023 , H01L2224/05548 , H01L2224/05568 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/1146 , H01L2224/131 , H01L2224/13147 , H01L2224/81203 , H01L2224/85048 , H01L2224/85205 , H01L2224/85207 , H01L2224/8581 , H01L2224/92 , H01L2224/9212 , H01L2224/94 , H01L2924/00014 , H01L2924/3512 , H01L2924/35121 , H01L2924/01013 , H01L2924/01029 , H01L2924/00012 , H01L2224/0231 , H01L2224/03 , H01L2924/014 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： An integrated circuit die includes a first bond pad having a bond contact area at a first depth into a plurality of build-up layers over a semiconductor substrate of the integrated circuit die, having sidewalls that surround the bond contact area, the sidewalls extending from the first depth to a top surface of the plurality of build-up layers, and having a top portion that extends over a portion of a top surface of the plurality of build-up layers.
摘要翻译： 集成电路管芯包括第一接合焊盘，该第一接合焊盘在集成电路管芯的半导体衬底上的第一深度处具有多个堆叠层中的接合区域，其具有包围接合区域的侧壁， 第一深度到多个堆积层的顶表面，并且具有在多个堆积层的顶表面的一部分上延伸的顶部。
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40.发明申请Semiconductor Manufacturing Using Disposable Test Circuitry Within Scribe Lanes 审中-公开半导体制造在标定车道内使用一次性测试电路公开(公告)号：US20150200146A1
公开(公告)日：2015-07-16
申请号：US14153417
申请日：2014-01-13
CPC分类号： H01L22/34 , H01L21/78 , H01L22/32 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： Embodiments are disclosed for semiconductor manufacturing using disposable test circuitry formed within scribe lanes. The manufacturing steps can include forming device circuitry within a semiconductor die and forming test circuitry within a scribe lane. One or more electrical connection route lines are also formed that connect the device circuitry and test circuitry blocks. Further, each die can be connected to a single test circuitry block, or multiple dice can share common test circuitry blocks. After testing, the electrical connection route line(s) are sealed, and the test circuitry is discarded when the device dice are singulated. For certain embodiments, the edge of the devices dice are encapsulated with a protective metal layer, and certain other embodiments include protective sealrings through which the connection route lines pass to enter the dice from the test circuitry blocks within the scribe lanes.
摘要翻译： 公开了使用在划线中形成的一次性测试电路的半导体制造的实施例。 制造步骤可以包括在半导体管芯内形成器件电路并在划线内形成测试电路。 还形成一个或多个连接设备电路和测试电路块的电连接路线。 此外，每个管芯可以连接到单个测试电路块，或者多个管芯可以共享公共测试电路块。 测试后，电气连接路线被密封，并且当设备裸片被切割时，测试电路被丢弃。 对于某些实施例，器件裸片的边缘被保护金属层封装，并且某些其它实施例包括保护性密封件，连接路线经过该保护密封件从划线中的测试电路块进入骰子。
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