公开(公告)号：US20170330862A1

公开(公告)日：2017-11-16

申请号：US15662764

申请日：2017-07-28

Applicant: Yeong-Hwan CHOE ,  Tae-Joo HWANG ,  Tae-Hong MIN ,  Young-Kun JEE ,  Sang-Uk HAN

Inventor： Yeong-Hwan CHOE ,  Tae-Joo HWANG ,  Tae-Hong MIN ,  Young-Kun JEE ,  Sang-Uk HAN

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/71 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/06156 ,  H01L2224/10125 ,  H01L2224/131 ,  H01L2224/14156 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75305 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor device includes at least first and second semiconductor chips stacked on each other along a first direction, at least one through-silicon-via (TSV) through at least the first semiconductor chip of the first and second semiconductor chips, a contact pad on the at least one TSV of the first semiconductor chip, the contact pad electrically connecting the TSV of the first semiconductor chip to the second semiconductor chip, and a plurality of dummy pads on the first semiconductor chip, the plurality of dummy pads being spaced apart from each other and from the contact pad along a second direction, and the dummy pads having same heights as the contact pads as measured between respective top and bottom surfaces along the first direction.

公开(公告)号：US08914941B2

公开(公告)日：2014-12-23

申请号：US13067415

申请日：2011-05-31

Applicant: Min-ha Kim ,  Joung-soo Park ,  Sung-tae Joo ,  Hyun-ju Lee ,  Dong-houn Yang

Inventor： Min-ha Kim ,  Joung-soo Park ,  Sung-tae Joo ,  Hyun-ju Lee ,  Dong-houn Yang

IPC: A47L9/16

CPC classification number: A47L9/1633 ,  A47L9/1641

Abstract: A cyclone dust collecting apparatus for a vacuum cleaner includes a first chamber; an entering passage disposed above the first chamber, the entering passage guiding outer air to form a downwardly whirling air current in the first chamber; a second chamber formed at a position higher than that of an outlet of the entering passage above the first chamber, the second chamber in which the outer air entering from the first chamber whirls; a contaminants-blocking member disposed to be spaced apart from a bottom surface of the first chamber at a center of the first chamber, the contaminants-blocking member preventing contaminants and water separated in the first chamber from moving into the second chamber; and a grill disposed inside the second chamber to be in fluid communication with an air discharging port through which clean air is discharged.

Abstract translation: 用于真空吸尘器的旋风除尘器包括：第一室; 进入通道，其设置在所述第一室的上方，所述进入通道引导外部空气以在所述第一室中形成向下旋转的气流; 第二室，其形成在比所述第一室上方的进入通道的出口高的位置处，从所述第一室进入的外部空气旋转的第二室; 污染物阻挡构件设置成在第一室的中心处与第一室的底表面间隔开，污染物阻挡构件防止在第一室中分离的污染物和水移动到第二室中; 以及设置在所述第二室内的格栅，以与排出空气的空气排出口流体连通。

公开(公告)号：US08729921B2

公开(公告)日：2014-05-20

申请号：US12878808

申请日：2010-09-09

Applicant: Seung Jei Yang ,  Myeong Ryeol Choi ,  Seung Yong Lee ,  Nam Deok Cho ,  Tae Joo Chang ,  Cheol Won Lee

Inventor： Seung Jei Yang ,  Myeong Ryeol Choi ,  Seung Yong Lee ,  Nam Deok Cho ,  Tae Joo Chang ,  Cheol Won Lee

IPC: G01R31/28

CPC classification number: G01R31/2805 ,  G01R31/2808 ,  G01R31/2815 ,  G01R31/318572

Abstract: A terminal discriminating apparatus and a terminal discriminating method using the same are provided. The terminal discriminating apparatus includes: a measurement unit for measuring a pull-up voltage and a pull-down voltage of each of candidate terminals to be discriminated; a discriminating unit for comparing the pull-up voltages, pull-down voltages, and the differences between the pull-up voltages and pull-down voltages for the candidate terminals to discriminate the types of the candidate terminals; and an output unit for outputting results of the discrimination of the candidate terminals transferred from the discriminating unit. The types of the candidate terminals can be discriminated by comparing the pull-up voltage, the pull-down voltage, and the differences between the pull-up voltages and the pull-down voltages for the candidate terminals.

Abstract translation: 提供了一种使用其的终端识别装置和终端鉴别方法。 终端识别装置包括：测量单元，用于测量待鉴别的候选终端的上拉电压和下拉电压; 鉴别单元，用于比较上拉电压，下拉电压以及候选终端的上拉电压和下拉电压之间的差异，以区分候选终端的类型; 以及输出单元，用于输出从识别单元传送的候选终端的辨别结果。 可以通过比较上拉电压，下拉电压以及候选终端的上拉电压和下拉电压之间的差异来鉴别候选终端的类型。

公开(公告)号：US20130200515A1

公开(公告)日：2013-08-08

申请号：US13785811

申请日：2013-03-05

Applicant: Tae-Joo HWANG ,  Tae-gyeong Chung ,  Eun-chul Ahn

Inventor： Tae-Joo HWANG ,  Tae-gyeong Chung ,  Eun-chul Ahn

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L23/481 ,  H01L24/06 ,  H01L24/16 ,  H01L24/29 ,  H01L24/31 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.

Abstract translation: 半导体封装包括第一封装衬底，设置在第一封装衬底上的第一半导体芯片，包括第一通孔通孔的半导体芯片和设置在第一半导体芯片上的芯片封装，芯片封装包括第二封装衬底和 设置在所述第二封装基板上的第二半导体芯片，其中，第一导电端子设置在所述半导体芯片的第一表面上，并且第二导电端子设置在所述第二封装基板的第一表面上，所述第一导电端子设置在所述第二封装基板的第二表面上 导电端子。

公开(公告)号：US20120167772A1

公开(公告)日：2012-07-05

申请号：US13392381

申请日：2010-06-21

Applicant: Min-Ha Kim ,  Joung-Soo Park ,  Heung-Jun Park ,  Sung-Tae Joo ,  Dong-Houn Yang

Inventor： Min-Ha Kim ,  Joung-Soo Park ,  Heung-Jun Park ,  Sung-Tae Joo ,  Dong-Houn Yang

IPC: B01D47/00

CPC classification number: A47L9/182 ,  A47L9/0072 ,  A47L9/1625 ,  A47L9/1666 ,  A47L9/186

Abstract: A wet-type dust collector for a vacuum cleaner. The disclosed wet-type dust collector includes a first separating portion, the inside of which is filled with water for separating dust from air that is suctioned in from the outside; an exhaust pipe unit having an exhaust outlet and installed inside the first separating portion; and a passage-closing unit installed inside the exhaust pipe unit, wherein the passage-closing unit closes the exhaust outlet of the exhaust pipe unit by means of the combined forces of the suctioning force through the exhaust pipe unit and the buoyant force of the water, in order to prevent the water from leaking out from the first separating portion.

Abstract translation: 用于吸尘器的湿式集尘器。 所公开的湿式集尘器包括：第一分离部分，其内部填充有用于从外部吸入的空气中分离的灰尘; 排气管单元，具有排气出口，并安装在第一分离部分的内部; 以及安装在所述排气管单元内的通道关闭单元，其中所述通过关闭单元借助于通过所述排气管单元的抽吸力和所述水的浮力的组合力来封闭所述排气管单元的排气出口 以防止水从第一分离部分泄漏出来。

公开(公告)号：US08178969B2

公开(公告)日：2012-05-15

申请号：US12401699

申请日：2009-03-11

Applicant: Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

Inventor： Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

IPC: H01L23/485

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05085 ,  H01L2224/05558 ,  H01L2224/0603 ,  H01L2224/06136 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.

Abstract translation: 倒装芯片封装可以包括衬底，半导体芯片，主凸块结构和辅助凸块结构。 基板具有电路图案。 半导体芯片布置在衬底上。 半导体芯片包括具有半导体结构的主体，与半导体结构电连接以主要控制半导体结构的主焊盘以及与半导体结构电连接以提供半导体结构的辅助控制的辅助焊盘。 主凸块结构插入在半导体芯片和基板之间以将电路图案与主焊盘电连接。 辅助凸块结构可以插入在半导体芯片和衬底之间以将电路图案与辅助焊盘电连接。

公开(公告)号：US07821139B2

公开(公告)日：2010-10-26

申请号：US11946750

申请日：2007-11-28

Applicant: Tae-Joo Hwang ,  Eun-Chul Ahn ,  Tae-Gyeong Chung

Inventor： Tae-Joo Hwang ,  Eun-Chul Ahn ,  Tae-Gyeong Chung

IPC: H01L31/00

CPC classification number: H01L24/90 ,  H01L23/3171 ,  H01L24/83 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A flip-chip assembly comprises a semiconductor chip, a substrate, a first buffer layer, a second buffer layer and a conductive bump. The semiconductor chip includes a first region and a second region adjacent to the first region. The substrate is disposed under the semiconductor chip. The first buffer layer is disposed between the first region of the semiconductor chip and the substrate. The second buffer layer is disposed between the second region of the semiconductor chip and the substrate. The conductive bump is formed through the second buffer layer and electrically connects the semiconductor chip to the substrate.

Abstract translation: 倒装芯片组件包括半导体芯片，衬底，第一缓冲层，第二缓冲层和导电凸块。 半导体芯片包括与第一区域相邻的第一区域和第二区域。 衬底设置在半导体芯片下方。 第一缓冲层设置在半导体芯片的第一区域和基板之间。 第二缓冲层设置在半导体芯片的第二区域和基板之间。 导电凸块通过第二缓冲层形成并将半导体芯片电连接到基板。

公开(公告)号：US20100008132A1

公开(公告)日：2010-01-14

申请号：US12397299

申请日：2009-03-03

Applicant: Cheol-Seong Hwang ,  Tae-Joo Park

Inventor： Cheol-Seong Hwang ,  Tae-Joo Park

IPC: G11C11/00 ,  H01L47/00 ,  G11C11/416

CPC classification number: H01L45/144 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

Abstract: A resistance memory element, a phase change memory element, a resistance random access memory device, an information reading method thereof, a phase change random access memory device, and an information reading method thereof are provided. The resistance random access memory device includes an array of resistance memory element arranged in a matrix. Each resistance memory element includes a substrate in which a source region and a drain region are formed along the column direction and a channel region is formed between the source region and the drain region, a bit line formed on the channel region out of a conductive material to have a shape extending along the arrangement direction of the columns, a resistance switching layer formed on the bit line out of a material of which electrical resistance is switched by an electrical signal, and a word line formed on the resistance switching layer out of a conductive material to have a shape extending along the row direction.

Abstract translation: 提供了电阻存储元件，相变存储元件，电阻随机存取存储器件，其信息读取方法，相变随机存取存储器件及其信息读取方法。 电阻随机存取存储器件包括以矩阵形式布置的电阻存储元件阵列。 每个电阻存储元件包括沿着列方向形成源极区和漏极区的衬底，并且在源区和漏区之间形成沟道区，形成在导电材料上的沟道区上的位线 具有沿着列的排列方向延伸的形状，形成在由电信号切换电阻的材料上的位线上的电阻切换层，以及形成在电阻切换层上的字线 导电材料具有沿着行方向延伸的形状。

公开(公告)号：US20090328194A1

公开(公告)日：2009-12-31

申请号：US12106427

申请日：2008-04-21

Applicant: Hyo Won Kim ,  Soo Hyeon Kim ,  Sun Kang ,  Tae Joo Chang

Inventor： Hyo Won Kim ,  Soo Hyeon Kim ,  Sun Kang ,  Tae Joo Chang

IPC: H04L9/32 ,  H04L12/28

CPC classification number: H04L63/0272 ,  H04L63/061 ,  H04L63/20

Abstract: Provided is an apparatus and method for virtual private network (VPN) communication in a socket level that can be applied in an Internet Protocol version 4 (IPv4)/IPv6 complex network, and can process data in a socket level to make a VPN communication apparatus available in many applications requiring more security, as well as a web application. The apparatus includes: a VPN database for storing connection information of an internal device and an external device and security-related information associated with the connection information; a packet analyzing module for analyzing a packet received from the internal device or the external device, obtaining connection information of the device, and storing the obtained connection information in the VPN database; a key exchange engine for performing a key sharing process with the device, generating the security-related information associated with the connection information, and storing the generated security-related information in the VPN database; and a socket data processing engine for encoding or decoding data in the socket level based on the security-related information stored in the VPN database, wherein the data is transmitted to and received from the internal device or the external device.

Abstract translation: 提供了一种可以应用在因特网协议版本4（IPv4）/ IPv6复杂网络中的套接字级别的虚拟专用网（VPN）通信的装置和方法，并且可以在套接字级别处理数据以形成VPN通信装置 可用于需要更多安全性的许多应用程序，以及Web应用程序。 该装置包括：VPN数据库，用于存储内部设备和外部设备的连接信息以及与连接信息相关联的安全相关信息; 分组分析模块，用于分析从内部设备或外部设备接收的分组，获得设备的连接信息，并将所获得的连接信息存储在VPN数据库中; 用于与所述设备执行密钥共享处理的密钥交换引擎，生成与所述连接信息相关联的安全相关信息，以及将所生成的安全相关信息存储在所述VPN数据库中; 以及插座数据处理引擎，用于基于存储在VPN数据库中的安全相关信息对套接字级别中的数据进行编码或解码，其中将数据发送到内部设备或外部设备并从其接收。

公开(公告)号：US20090230549A1

公开(公告)日：2009-09-17

申请号：US12401699

申请日：2009-03-11

Applicant: Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

Inventor： Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

IPC: H01L23/485

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05085 ,  H01L2224/05558 ,  H01L2224/0603 ,  H01L2224/06136 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.

Abstract translation: 倒装芯片封装可以包括衬底，半导体芯片，主凸块结构和辅助凸块结构。 基板具有电路图案。 半导体芯片布置在衬底上。 半导体芯片包括具有半导体结构的主体，与半导体结构电连接以主要控制半导体结构的主焊盘以及与半导体结构电连接以提供半导体结构的辅助控制的辅助焊盘。 主凸块结构插入在半导体芯片和基板之间以将电路图案与主焊盘电连接。 辅助凸块结构可以插入在半导体芯片和衬底之间以将电路图案与辅助焊盘电连接。