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公开(公告)号：US20070099123A1
公开(公告)日：2007-05-03
申请号：US11307425
申请日：2006-02-07
Applicant: Tzyy-Jang Tseng , Cheng-Po Yu
Inventor： Tzyy-Jang Tseng , Cheng-Po Yu
IPC: G03C5/00
CPC classification number: H05K3/28 , H05K3/3452 , H05K2203/013 , H05K2203/0557 , H05K2203/058 , H05K2203/1476
Abstract: A method of forming solder mask, suitable for forming a solder mask on the surface of a wiring board, is provided. The surface of the wiring board includes a first region and a second region, and the surface of the wiring board has a wiring pattern thereon. The method includes forming a first sub solder mask in the first region on the surface of the wiring board by performing a screen-printing or a photolithographic process, and forming a second sub solder mask in the second region on the surface of the wiring board by performing an ink-jet printing process. The method not only improves the precision of the solder mask alignment on the wiring board and its reliability, but also increases the production rate and lowers the manufacturing cost.
Abstract translation: 提供一种形成焊接掩模的方法，该方法适用于在布线板的表面上形成焊接掩模。 布线板的表面包括第一区域和第二区域，并且布线板的表面上具有布线图案。 该方法包括通过丝网印刷或光刻工艺在布线板的表面上的第一区域中形成第一子焊料掩模，并且在布线板的表面上的第二区域中形成第二副焊料掩模 进行喷墨打印处理。 该方法不仅提高了布线板上的焊盘对准的精度及其可靠性，而且提高了生产率，降低了制造成本。
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公开(公告)号：US09131614B2
公开(公告)日：2015-09-08
申请号：US13620431
申请日：2012-09-14
Applicant: Cheng-Po Yu , Chai-Liang Hsu
Inventor： Cheng-Po Yu , Chai-Liang Hsu
CPC classification number: H05K3/107 , H05K3/181 , H05K3/422 , H05K2201/0376
Abstract: A method for manufacturing an embedded wiring board is provided. An activating insulation layer is formed. The activating insulation layer includes a plurality of catalyst particles, and covers a first wiring layer. An intaglio pattern and at least one blind via partially exposing the first wiring layer are formed on the activating insulation layer, in which some of the catalyst particles are activated and exposed in the intaglio pattern and the blind via. The activating insulation layer is dipped in a first chemical plating solution, and a solid conductive pillar is formed in the blind via through electroless plating. The activating insulation layer is dipped in a second chemical plating solution after the solid conductive pillar is formed, and a second wiring layer is formed in the intaglio pattern through the electroless plating. Components of the first chemical plating solution and the second chemical plating solution are different.
Abstract translation: 提供了一种用于制造嵌入式布线板的方法。 形成激活绝缘层。 激活绝缘层包括多个催化剂颗粒，并且覆盖第一布线层。 在活化绝缘层上形成凹版图案和部分露出第一布线层的至少一个盲孔，其中一些催化剂颗粒被活化并以凹版图案和盲孔曝光。 将激活绝缘层浸入第一化学镀溶液中，并通过化学镀在盲孔中形成固体导电柱。 在形成固体导电柱之后，将激活绝缘层浸入第二化学镀溶液中，并且通过无电解电镀在凹版图案中形成第二布线层。 第一化学镀液和第二化学镀液的成分不同。
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公开(公告)号：US20140041919A1
公开(公告)日：2014-02-13
申请号：US13615722
申请日：2012-09-14
Applicant: Shang-Feng Huang , Cheng-Po Yu , Jen-Chi Cheng
Inventor： Shang-Feng Huang , Cheng-Po Yu , Jen-Chi Cheng
CPC classification number: H05K1/0221 , H05K3/4644 , Y10T29/49155
Abstract: A circuit structure includes an inner circuit layer, a first and a second dielectric layers, a first and a second conductive material layers, and a second and a third conductive layers. The first dielectric layer covers a first conductive layer of the inner circuit layer and has a first surface and first circuit grooves. The first conductive material layer is disposed inside the first circuit grooves. The second conductive layer is disposed on the first surface and includes a signal trace and at least two reference traces. The second dielectric layer covers the first surface and the second conductive layer and has a second surface and second circuit grooves. Widths of the first and the second circuit grooves are smaller than that of the reference traces. The second conductive material layer is disposed inside the second circuit grooves. The third conductive layer is disposed on the second surface.
Abstract translation: 电路结构包括内部电路层，第一和第二电介质层，第一和第二导电材料层以及第二和第三导电层。 第一电介质层覆盖内电路层的第一导电层，并具有第一表面和第一电路槽。 第一导电材料层设置在第一电路槽的内部。 第二导电层设置在第一表面上并且包括信号迹线和至少两个参考迹线。 第二电介质层覆盖第一表面和第二导电层，并具有第二表面和第二电路槽。 第一和第二电路槽的宽度小于参考轨迹的宽度。 第二导电材料层设置在第二电路槽的内部。 第三导电层设置在第二表面上。
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公开(公告)号：US20130327564A1
公开(公告)日：2013-12-12
申请号：US13570251
申请日：2012-08-09
Applicant: Cheng-Po Yu , Shang-Feng Huang , Chang-Ming Lee , Young-Sheng Bai
Inventor： Cheng-Po Yu , Shang-Feng Huang , Chang-Ming Lee , Young-Sheng Bai
CPC classification number: H05K3/381 , H05K3/105 , H05K3/108 , H05K2201/0215 , H05K2201/09563 , H05K2203/0307 , H05K2203/095 , H05K2203/1461
Abstract: A circuit board and a manufacturing method thereof are provided. According to the method, a dielectric layer is formed on a dielectric substrate, and the dielectric layer contains active particles. A surface treatment is performed on a surface of the dielectric first conductive layer is formed on the activated surface of the dielectric layer. A conductive via is formed in the dielectric substrate and the dielectric layer. A patterned mask layer is formed on the first conductive layer, in which the patterned mask layer exposes the conductive via and a part of the first conductive layer. A second conductive layer is formed on the first conductive layer and conductive via exposed by the patterned mask layer. The patterned mask layer and the first conductive layer below the patterned mask layer are removed.
Abstract translation: 提供一种电路板及其制造方法。 根据该方法，在电介质基板上形成介电层，电介质层含有活性粒子。 在电介质层的活化表面上形成电介质第一导电层的表面进行表面处理。 在电介质基板和电介质层中形成导电通孔。 图案化的掩模层形成在第一导电层上，其中图案化掩模层暴露导电通孔和第一导电层的一部分。 在第一导电层上形成第二导电层，并且由图案化掩模层暴露出导电通路。 图案化掩模层和图案化掩模层下面的第一导电层被去除。
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公开(公告)号：US08166652B2
公开(公告)日：2012-05-01
申请号：US12270718
申请日：2008-11-13
Applicant: Cheng-Po Yu
Inventor： Cheng-Po Yu
IPC: H05K3/10
CPC classification number: H05K3/107 , H05K1/0265 , H05K3/0032 , H05K3/06 , H05K3/061 , H05K2201/0376 , H05K2201/09727 , H05K2203/0369 , Y10T29/49117 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
Abstract: A circuit structure of a circuit board includes a dielectric layer, a number of first circuits, and a number of second circuits. The dielectric layer has a surface and an intaglio pattern. The first circuits are disposed on the surface of the dielectric layer. The second circuits are disposed in the intaglio pattern of the dielectric layer. Line widths of the second circuits are smaller than line widths of the first circuits, and a distance between every two of the adjacent second circuits is shorter than a distance between every two of the adjacent first circuits.
Abstract translation: 电路板的电路结构包括电介质层，多个第一电路和多个第二电路。 电介质层具有表面和凹版图案。 第一电路设置在电介质层的表面上。 第二电路设置在电介质层的凹版图案中。 第二电路的线宽小于第一电路的线宽，并且相邻的第二电路中的每两个之间的距离比相邻的第一电路中的每两个之间的距离短。
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Patent Agency Ranking
公开(公告)号：US08161638B2
公开(公告)日：2012-04-24
申请号：US12783806
申请日：2010-05-20
Applicant: Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
Inventor： Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
IPC: H01K3/10
CPC classification number: H05K3/465 , H05K3/0032 , H05K3/0035 , H05K3/184 , H05K3/421 , H05K3/4661 , H05K2201/0166 , H05K2201/0195 , H05K2203/1152 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T156/1056
Abstract: A manufacturing method of circuit structure is described as follows. Firstly, a composite dielectric layer, a circuit board and an insulating layer disposed therebetween are provided. The composite dielectric layer includes a non-platable dielectric layer and a platable dielectric layer between the non-platable dielectric layer and the insulating layer wherein the non-platable dielectric layer includes a chemical non-platable material and the platable dielectric layer includes a chemical platable material. Then, the composite dielectric layer, the circuit board and the insulating layer are compressed. Subsequently, a through hole passing through the composite dielectric layer and the insulating layer is formed and a conductive via connecting a circuit layer of the circuit board is formed therein. Then, a trench pattern passing through the non-platable dielectric layer is formed on the composite dielectric layer. Subsequently, a chemical plating process is performed to form a conductive pattern in the trench pattern.
Abstract translation: 电路结构的制造方法如下所述。 首先，提供复合电介质层，电路基板和设置在它们之间的绝缘层。 复合电介质层包括不可镀介电层和介于非平板电介质层和绝缘层之间的可镀介电层，其中非可镀介电层包括化学不可镀材料，并且可镀介电层包括化学镀层 材料。 然后，复合介电层，电路板和绝缘层被压缩。 随后，形成穿过复合介电层和绝缘层的通孔，并且在其中形成连接电路板的电路层的导电通孔。 然后，在复合电介质层上形成通过非电介质层的沟槽图案。 随后，执行化学镀处理以在沟槽图案中形成导电图案。
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公开(公告)号：US20120060368A1
公开(公告)日：2012-03-15
申请号：US13301812
申请日：2011-11-22
Applicant: Cheng-Po Yu , Han-Pei Huang
Inventor： Cheng-Po Yu , Han-Pei Huang
IPC: H05K3/22
CPC classification number: H05K1/11 , H05K1/0284 , H05K1/142 , H05K3/185 , H05K3/4007 , H05K3/4661 , H05K2201/0236 , H05K2201/09045 , H05K2201/09118 , H05K2201/09163 , H05K2201/09436 , H05K2201/09509 , H05K2201/09845 , H05K2203/1327 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49158 , Y10T428/24802 , Y10T428/24917
Abstract: A method of fabrication a circuit board structure comprising providing a circuit board main body, forming a molded, irregular plastic body having a non-plate type, stereo structure and at least one scraggy surface by encapsulating at least a portion of said circuit board main body with injection molded material, and forming a first three-dimensional circuit pattern on said molded, irregular plastic body thereby defining a three-dimensional circuit device.
Abstract translation: 一种制造电路板结构的方法，包括提供电路板主体，通过封装所述电路板主体的至少一部分来形成具有非板型，立体结构和至少一个刮痕表面的模制的不规则塑料体 并且在所述模制的不规则塑料体上形成第一三维电路图案，从而限定三维电路装置。
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公开(公告)号：US20110100543A1
公开(公告)日：2011-05-05
申请号：US12783806
申请日：2010-05-20
Applicant: Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
Inventor： Tzyy-Jang Tseng , Chang-Ming Lee , Wen-Fang Liu , Cheng-Po Yu
CPC classification number: H05K3/465 , H05K3/0032 , H05K3/0035 , H05K3/184 , H05K3/421 , H05K3/4661 , H05K2201/0166 , H05K2201/0195 , H05K2203/1152 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T156/1056
Abstract: A manufacturing method of circuit structure is described as follows. Firstly, a composite dielectric layer, a circuit board and an insulating layer disposed therebetween are provided. The composite dielectric layer includes a non-platable dielectric layer and a platable dielectric layer between the non-platable dielectric layer and the insulating layer wherein the non-platable dielectric layer includes a chemical non-platable material and the platable dielectric layer includes a chemical platable material. Then, the composite dielectric layer, the circuit board and the insulating layer are compressed. Subsequently, a through hole passing through the composite dielectric layer and the insulating layer is formed and a conductive via connecting a circuit layer of the circuit board is formed therein. Then, a trench pattern passing through the non-platable dielectric layer is formed on the composite dielectric layer. Subsequently, a chemical plating process is performed to form a conductive pattern in the trench pattern.
Abstract translation: 电路结构的制造方法如下所述。 首先，提供复合电介质层，电路基板和设置在它们之间的绝缘层。 复合电介质层包括不可镀介电层和介于非平板电介质层和绝缘层之间的可镀介电层，其中非可镀介电层包括化学不可镀材料，并且可镀介电层包括化学镀层 材料。 然后，复合介电层，电路板和绝缘层被压缩。 随后，形成穿过复合介电层和绝缘层的通孔，并且在其中形成连接电路板的电路层的导电通孔。 然后，在复合电介质层上形成通过非电介质层的沟槽图案。 随后，执行化学镀处理以在沟槽图案中形成导电图案。
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公开(公告)号：US20100065319A1
公开(公告)日：2010-03-18
申请号：US12328446
申请日：2008-12-04
Applicant: Tsung-Yuan Chen , Chun-Chien Chen , Cheng-Po Yu
Inventor： Tsung-Yuan Chen , Chun-Chien Chen , Cheng-Po Yu
CPC classification number: H05K3/428 , H05K3/0032 , H05K3/0035 , H05K3/0038 , H05K3/20 , H05K3/205 , H05K2201/09509 , H05K2201/09563 , H05K2201/0969 , H05K2203/0369 , H05K2203/0376 , H05K2203/0384 , H05K2203/0554 , H05K2203/108 , H05K2203/1476 , Y10T29/49124 , Y10T29/49126
Abstract: A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed.
Abstract translation: 提供一种制造布线板的工艺。 在该过程中，形成包括携带衬底和布线层的布线承载衬底。 接下来，在布线承载基板中形成至少一个盲孔。 接下来，通过绝缘层将布线承载基板层叠到另一布线承载基板。 绝缘层设置在布线基板的布线层之间，并且完全填充盲孔。 接下来，去除部分搬运基板以露出盲孔中的绝缘层。 接下来，形成连接在布线层之间的导电柱。 接下来，其余的携带衬底被去除。
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公开(公告)号：US20090250247A1
公开(公告)日：2009-10-08
申请号：US12170082
申请日：2008-07-09
Applicant: Cheng-Po Yu , Cheng-Hung Yu
Inventor： Cheng-Po Yu , Cheng-Hung Yu
CPC classification number: H05K1/0231 , H05K1/0219 , H05K1/162 , H05K3/107 , H05K2201/09036 , H05K2201/09809 , Y10T29/49117
Abstract: A circuit board including a first dielectric layer having a first surface and a second surface, a first circuit layer, a second dielectric layer, and a second circuit layer is provided. At least one trench is formed on the first surface, and the first circuit layer is formed on an inside wall of the trench. In addition, the second dielectric layer is disposed in the trench, and covers the first circuit layer. The second circuit layer is disposed in the trench, and the second dielectric layer is located between the first circuit layer and the second circuit layer. A manufacturing method of the circuit board is further provided.
Abstract translation: 提供一种电路板，包括具有第一表面和第二表面的第一介电层，第一电路层，第二电介质层和第二电路层。 在第一表面上形成至少一个沟槽，并且第一电路层形成在沟槽的内壁上。 此外，第二电介质层设置在沟槽中并覆盖第一电路层。 第二电路层设置在沟槽中，第二电介质层位于第一电路层和第二电路层之间。 还提供了电路板的制造方法。
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