公开(公告)号：US09455204B1

公开(公告)日：2016-09-27

申请号：US14727143

申请日：2015-06-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy M. Cao ,  Jinping Liu ,  Guillaume Bouche ,  Huang Liu

IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823892 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

Abstract: A method of introducing N/P dopants in PMOS and NMOS fins at the SSRW layer without complicated processing and the resulting device are provided. Embodiments include forming a plurality of p-type and n-type fins on a substrate, the plurality of p-type and n-type fins formed with an ISSG or pad oxide layer; performing an n-well implant into the substrate through the ISSG or pad oxide layer; performing a first SRPD on the ISSG or pad oxide layer of the plurality of p-type fins; performing a p-well implant into the substrate through the ISSG or pad oxide layer; performing a second SRPD on the ISSG or pad oxide layer of the plurality of n-type fins; and driving the n-well and p-well implants and the SRPD dopants into a portion of the plurality of p-type and n-type fins.

Abstract translation: 在SSRW层的PMOS和NMOS鳍片中引入N / P掺杂剂而不需要复杂的处理并提供所得到的器件的方法。 实施例包括在基板上形成多个p型和n型翅片，多个p型和n型翅片形成有ISSG或衬垫氧化物层; 通过ISSG或衬垫氧化物层将n阱注入到衬底中; 在多个p型翅片的ISSG或衬垫氧化物层上执行第一SRPD; 通过ISSG或垫氧化物层进行p阱注入到衬底中; 在所述多个n型鳍片的ISSG或衬垫氧化物层上执行第二SRPD; 并且将n阱和p阱注入和SRPD掺杂剂驱动到多个p型和n型鳍中的一部分中。

公开(公告)号：US09330982B1

公开(公告)日：2016-05-03

申请号：US14826276

申请日：2015-08-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy Cao ,  Songkram Srivathanakul ,  Jinping Liu ,  In Soo Jung

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/2255 ,  H01L21/823821 ,  H01L27/0924

Abstract: A method of forming a diffusion barrier film over fins and the resulting device are provided. Embodiments include forming silicon fins over a substrate; depositing a borosilicate glass (BSG) liner cap over a first set of the silicon fins; depositing a phosphosilicate (PSG) liner cap over a second set of the silicon fins; and depositing a silicon oxycarbide (SiOC) diffusion barrier film over the BSG and PSG liner caps.

Abstract translation: 提供了一种在翅片上形成扩散阻挡膜的方法和所得到的器件。 实施例包括在衬底上形成硅散热片; 在第一组硅片上沉积硼硅酸盐玻璃（BSG）衬垫帽; 在第二组硅片上沉积磷硅酸盐（PSG）衬垫帽; 并在BSG和PSG衬套上沉积硅碳氧化物（SiOC）扩散阻挡膜。

公开(公告)号：US20150380502A1

公开(公告)日：2015-12-31

申请号：US14849335

申请日：2015-09-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Jinping Liu

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/41791 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/401 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Embodiments of the present invention provide an improved contact formation process for a finFET. Epitaxial semiconductor regions are formed on the fins. A contact etch stop layer (CESL) is deposited on the epitaxial regions. A nitride-oxide conversion process converts a portion of the nitride CESL into oxide. The oxide-converted portions are removed using a selective etch process, and a fill metal is deposited which is in direct physical contact with the epitaxial regions. Damage, such as gouging, of the epitaxial regions is minimized during this process, resulting in an improved contact for finFETs.

公开(公告)号：US09165767B2

公开(公告)日：2015-10-20

申请号：US14071170

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bharat Krishnan ,  Jody A. Fronheiser ,  Jinping Liu ,  Bongki Lee

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L21/823431 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/324 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor structure includes a bulk silicon substrate and one or more silicon fins coupled to the bulk silicon substrate. Stress-inducing material(s), such as silicon, are epitaxially grown on the fins into naturally diamond-shaped structures using a controlled selective epitaxial growth. The diamond shaped structures are subjected to annealing at about 750° C. to about 850° C. to increase an area of (100) surface orientation by reshaping the shaped structures from the annealing. Additional epitaxy is grown on the increased (100) area. Multiple cycles of increasing the area of (100) surface orientation (e.g., by the annealing) and growing additional epitaxy on the increased area are performed to decrease the width of the shaped structures, increasing the space between them to prevent them from merging, while also increasing their volume.

Abstract translation: 半导体结构包括体硅衬底和耦合到体硅衬底的一个或多个硅散热片。 使用受控的选择性外延生长，诸如硅的应力诱导材料在翅片上外延生长成天然的菱形结构。 金刚石结构在约750℃至约850℃下进行退火，以通过从退火中重塑成形结构来增加（100）表面取向的面积。 额外的外延生长在增加的（100）区域。 进行增加（100）表面取向（例如通过退火）的面积和在增加的面积上生长附加外延的多个循环以减小成形结构的宽度，增加它们之间的空间以防止它们的合并，同时 也增加了他们的体积。

公开(公告)号：US20150061027A1

公开(公告)日：2015-03-05

申请号：US14017485

申请日：2013-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

IPC: H01L27/092 ,  H01L21/28

CPC classification number: H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

Abstract translation: 用于形成用于NMOS和PMOS晶体管的替代栅极结构的一种方法包括执行蚀刻工艺以去除用于NMOS和PMOS晶体管的牺牲栅极结构，由此限定NMOS和PMOS栅极腔，在栅极腔中沉积栅极绝缘层， 在栅极腔中的栅极绝缘层上的第一金属层，执行至少一个处理操作以在NMOS栅极腔内的第一金属层上方形成（1）NMOS金属硅化物材料，所述NMOS金属硅化物材料具有第一量 原子硅，和（2）在PMOS栅极腔内的第一金属层上方的PMOS金属硅化物材料，PMOS金属硅化物材料具有第二量的原子硅，并且其中第一和第二量的原子硅是不同的，以及 在NMOS和PMOS门腔内形成栅极盖层。

公开(公告)号：US20140159052A1

公开(公告)日：2014-06-12

申请号：US13710639

申请日：2012-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinping Liu ,  Yi Qi ,  Xiaodong Yang

IPC: H01L29/78 ,  H01L21/02

CPC classification number: H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: Embodiments of the invention provide an improved method and structure for a transistor with reduced DIBL and RON. A sigma cavity is formed in a semiconductor substrate adjacent to a transistor. The sigma cavity is filled with an epitaxially grown semiconductor material that also serves as a stress-inducing region for the purposes of increasing carrier mobility. The epitaxially grown semiconductor material is doped with a reverse doping profile. A lightly doped region lines the interior of the sigma cavity, followed by an undoped region, followed by a heavily doped region. The shape of the lightly doped region is such that it is thicker adjacent to the channel, which reduces RON, and thinner below the channel, which reduces DIBL.

Abstract translation: 本发明的实施例提供了具有减少的DIBL和RON的晶体管的改进的方法和结构。 在与晶体管相邻的半导体衬底中形成Σ腔。 填充有外延生长的半导体材料，其也用作应力诱导区域，以增加载流子迁移率。 外延生长的半导体材料掺杂有反向掺杂分布。 轻掺杂区域将西格玛腔体的内部引导，随后是未掺杂的区域，随后是重掺杂区域。 轻掺杂区域的形状使其在沟道附近较厚，这降低了RON，并且在沟道以下更薄，这降低了DIBL。

公开(公告)号：US20140120708A1

公开(公告)日：2014-05-01

申请号：US13664744

申请日：2012-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Min Dai ,  Xiang Hu ,  Jinping Liu ,  Yanxiang Liu ,  Xiaodong Yang

IPC: H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/2807 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823462

Abstract: A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.

Abstract translation: 公开了一种制造半导体器件的方法，该半导体器件包括结合导电虚拟栅极层（例如硅锗（SiGe），氮化钛等）的替代金属栅极工艺）和相关的方法。 该方法包括在衬底上形成氧化物层; 在所述半导体器件的第一区域中从所述衬底去除所述氧化物层的栅极部分; 在所述第一区域中的所述半导体器件上形成导电虚拟栅极层; 以及在所述半导体器件上形成栅极，所述栅极包括设置在所述第一区域中并直接连接到所述衬底的栅极导体。

公开(公告)号：US10910471B2

公开(公告)日：2021-02-02

申请号：US16032878

申请日：2018-07-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jianwei Peng ,  Sang Woo Lim ,  Matthew Wahlquist Stoker ,  Huang Liu ,  Jinping Liu

IPC: H01L29/76 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/092

Abstract: A method of forming a logic or memory cell with an epi-RSD width of larger than 1.3× fin pitch and the resulting device are provided. Embodiments include a device including a RSD region formed on each of a plurality of fins over a substrate, wherein the RSD has a width larger than 1.3× fin pitch, a TS formed on the RSD, and an ILD formed over the TS.

公开(公告)号：US10784195B2

公开(公告)日：2020-09-22

申请号：US15959727

申请日：2018-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Xiaoqiang Zhang ,  Haizhou Yin ,  Moosung M. Chae ,  Jinping Liu ,  Hui Zang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/525

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.

公开(公告)号：US10566195B2

公开(公告)日：2020-02-18

申请号：US15689668

申请日：2017-08-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Jinping Liu ,  Rui Chen

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/768

Abstract: Methods of multiple patterning. First and second mandrel lines are formed on a patternable layer. Sidewall spacers are formed on the patternable layer adjacent to the first mandrel line and adjacent to the second mandrel line. A portion of the first mandrel line is removed to form a gap in the first mandrel line. A gapfill material is deposited in the gap in the first mandrel line. The gapfill material and sidewall spacers are composed of the same material.