公开(公告)号：US09735154B2

公开(公告)日：2017-08-15

申请号：US14918012

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Dae-han Choi ,  Dae Geun Yang ,  Xiang Hu ,  Mariappan Hariharaputhiran

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/308 ,  H01L21/311 ,  H01L21/306 ,  H01L21/762 ,  H01L21/033 ,  H01L21/475 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/475 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.

公开(公告)号：US09666476B2

公开(公告)日：2017-05-30

申请号：US14969154

申请日：2015-12-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang Hu ,  Yuping Ren ,  Duohui Bei ,  Sipeng Gu ,  Huang Liu

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/538 ,  H01L21/311 ,  H01L21/02 ,  H01L21/308 ,  H01L23/522

CPC classification number: H01L21/76816 ,  H01L21/02063 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench.

公开(公告)号：US09490129B2

公开(公告)日：2016-11-08

申请号：US14272952

申请日：2014-05-08

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xiang Hu ,  Huang Liu

IPC: H01L21/336 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/088

CPC classification number: H01L21/28123 ,  H01L21/28035 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3213 ,  H01L21/32133 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/49 ,  H01L29/4916 ,  H01L29/66 ,  H01L29/66553 ,  H01L29/6681

Abstract: Integrated circuits with improved gate structures and methods for fabricating integrated circuits with improved gate structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures. A gate-forming material is deposited over the semiconductor substrate and fin structures. The method includes performing a first etch process to etch the gate-forming material to form a gate line having a first side and a second side. The first side and second side of the gate line are bounded with material. The method includes performing a second etch process to etch a portion of the gate line bound by the material to separate the gate line into adjacent gate structures and to define a tip-to-tip distance between the adjacent gate structures.

Abstract translation: 提供了具有改进的栅极结构的集成电路和用于制造具有改进的栅极结构的集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供具有鳍结构的半导体衬底。 栅极形成材料沉积在半导体衬底和鳍结构上。 该方法包括执行第一蚀刻工艺以蚀刻栅极形成材料以形成具有第一侧和第二侧的栅极线。 栅极线的第一侧和第二侧与材料有界。 该方法包括执行第二蚀刻工艺以蚀刻由材料限定的栅极线的一部分，以将栅极线分离成相邻的栅极结构并且限定相邻栅极结构之间的尖端到尖端的距离。

公开(公告)号：US09431528B2

公开(公告)日：2016-08-30

申请号：US14281359

申请日：2014-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Xiang Hu ,  Zhao Lun ,  Huang Liu

IPC: H01L21/311 ,  H01L29/06 ,  H01L29/12 ,  H01L29/78 ,  H01L21/3105 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/78 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/3105 ,  H01L21/31051 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L29/0684 ,  H01L29/12 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A lithographic stack over a raised structure (e.g., fin) of a non-planar semiconductor structure, such as a FinFET, includes a bottom layer of spin-on amorphous carbon or spin-on organic planarizing material, a hard mask layer of a nitride and/or an oxide on the spin-on layer, a layer of a developable bottom anti-reflective coating (dBARC) on the hard mask layer, and a top layer of photoresist. The stack is etched to expose and recess the raised structure, and epitaxial structure(s) are grown on the recess.

Abstract translation: 诸如FinFET的非平面半导体结构的凸起结构（例如，翅片）上的光刻叠层包括旋涂非晶碳或旋涂有机平面化材料的底层，氮化物的硬掩模层 和/或旋涂层上的氧化物，硬掩模层上的可显影底部抗反射涂层（dBARC）的层和光致抗蚀剂的顶层。 蚀刻该叠层以露出和凹进凸起的结构，并且外延结构在凹槽上生长。

公开(公告)号：US09401263B2

公开(公告)日：2016-07-26

申请号：US14031563

申请日：2013-09-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang Hu ,  Gabriel Padron Wells ,  Jack Chao-Hsu Chang ,  Mingmei Wang ,  Taejoon Han

IPC: H01J37/32 ,  H01L21/3065 ,  H01L21/3213

CPC classification number: H01J37/32146 ,  H01J37/32174 ,  H01J2237/3341 ,  H01J2237/3348 ,  H01L21/3065 ,  H01L21/32137

Abstract: Etching a feature of a structure by an etch system is facilitated by varying supply of radio frequency (RF) power pulses to the etch system. The varying provides at least one RF power pulse, of the supplied RF power pulses, that deviates from one or more other RF power pulses, of the supplied RF power pulses, by at least one characteristic.

Abstract translation: 通过改变对蚀刻系统的射频（RF）功率脉冲的供应，便于蚀刻系统蚀刻结构的特征。 变化通过至少一个特征提供所提供的RF功率脉冲中提供的RF功率脉冲的至少一个RF功率脉冲，其偏离所提供的RF功率脉冲的一个或多个其它RF功率脉冲。

公开(公告)号：US09305785B2

公开(公告)日：2016-04-05

申请号：US14318901

申请日：2014-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Gabriel Padron Wells ,  Xiang Hu

IPC: H01L27/088 ,  H01L21/28 ,  H01L29/06 ,  H01L23/535 ,  H01L21/762 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L21/28008 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an improved structure and method of contact formation. A cap nitride is removed from a gate in a region that is distanced from a fin. This facilitates reduced process steps, allowing the gate and the source/drain regions to be opened in the same process step. Extreme Ultraviolet Lithography (EUVL) may be used to pattern the resist to form the contacts.

Abstract translation: 本发明的实施例提供了改进的接触形成的结构和方法。 在与翅片间隔开的区域中，从栅极去除顶盖氮化物。 这有助于减少处理步骤，允许栅极和源极/漏极区域以相同的工艺步骤打开。 可以使用极紫外光刻（EUVL）来形成抗蚀剂以形成接触。

公开(公告)号：US09281249B2

公开(公告)日：2016-03-08

申请号：US14155504

申请日：2014-01-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alok Vaid ,  Abner Bello ,  Sipeng Gu ,  Lokesh Subramany ,  Xiang Hu ,  Akshey Sehgal

IPC: H01L21/66 ,  G01B11/02 ,  G01B11/06 ,  G03F7/20 ,  G01N21/21

CPC classification number: H01L22/12 ,  G01B11/02 ,  G01B11/0633 ,  G01B11/065 ,  G01B2210/56 ,  G01N21/211 ,  G03F7/70616 ,  G03F7/70625

Abstract: Measurement of thickness of layers of a circuit structure is obtained, where the thickness of the layers is measured using an optical critical dimension (OCD) measurement technique, and the layers includes a high-k layer and an interfacial layer. Measurement of thickness of the high-k layer is separately obtained, where the thickness of the high-k layer is measured using a separate measurement technique from the OCD measurement technique. The separate measurement technique provides greater decoupling, as compared to the OCD measurement technique, of a signal for thickness of the high-k layer from a signal for thickness of the interfacial layer of the layers. Characteristics of the circuit structure, such as a thickness of the interfacial layer, are ascertained using, in part, the separately obtained thickness measurement of the high-k layer.

Abstract translation: 获得电路结构层的厚度的测量，其中使用光学临界尺寸（OCD）测量技术测量层的厚度，并且层包括高k层和界面层。 分别获得高k层的厚度的测量，其中使用来自OCD测量技术的单独的测量技术来测量高k层的厚度。 与OCD测量技术相比，单独的测量技术提供了来自层的界面层厚度的信号的高k层厚度的信号的更大的去耦。 电路结构的特性，如界面层的厚度，部分使用单独获得的高k层的厚度测量来确定。

公开(公告)号：US20150325482A1

公开(公告)日：2015-11-12

申请号：US14272952

申请日：2014-05-08

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xiang Hu ,  Huang Liu

IPC: H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/088 ,  H01L21/308

CPC classification number: H01L21/28123 ,  H01L21/28035 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3213 ,  H01L21/32133 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/49 ,  H01L29/4916 ,  H01L29/66 ,  H01L29/66553 ,  H01L29/6681

Abstract: Integrated circuits with improved gate structures and methods for fabricating integrated circuits with improved gate structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures. A gate-forming material is deposited over the semiconductor substrate and fin structures. The method includes performing a first etch process to etch the gate-forming material to form a gate line having a first side and a second side. The first side and second side of the gate line are bounded with material. The method includes performing a second etch process to etch a portion of the gate line bound by the material to separate the gate line into adjacent gate structures and to define a tip-to-tip distance between the adjacent gate structures.

Abstract translation: 提供了具有改进的栅极结构的集成电路和用于制造具有改进的栅极结构的集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供具有鳍结构的半导体衬底。 栅极形成材料沉积在半导体衬底和鳍结构上。 该方法包括执行第一蚀刻工艺以蚀刻栅极形成材料以形成具有第一侧和第二侧的栅极线。 栅极线的第一侧和第二侧与材料有界。 该方法包括执行第二蚀刻工艺以蚀刻由材料限定的栅极线的一部分，以将栅极线分离成相邻的栅极结构并且限定相邻栅极结构之间的尖端到尖端的距离。

公开(公告)号：US20150279684A1

公开(公告)日：2015-10-01

申请号：US14225542

申请日：2014-03-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andy Chih-Hung Wei ,  Dae-han Choi ,  Dae Geun Yang ,  Xiang Hu ,  Mariappan Hariharaputhiran

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L21/306

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/475 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.

Abstract translation: 本发明的实施例提供了从finFET去除翅片部分的方法。 在起始点，高K电介质层设置在基板上。 翅片硬掩模和光刻叠层沉积在高k电介质上。 翅片硬掩模被暴露，并且鳍状硬标记的第一部分被去除。 去除光刻叠层。 拆下散热片硬掩模的第二部分。 鳍形成。 间隙填充电介质被沉积并凹进。

公开(公告)号：US09129905B2

公开(公告)日：2015-09-08

申请号：US14070624

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang Hu ,  Lokesh Subramany ,  Alok Vaid ,  Sipeng Gu ,  Akshey Sehgal

IPC: H01L21/308 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/544 ,  H01L21/3083 ,  H01L21/3086 ,  H01L22/30 ,  H01L27/0886 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.

Abstract translation: 公开了一种用于提供与翅片场效应晶体管（FinFET）器件的一组翅片相邻的平面计量垫的方法。 先前沉积的非晶碳层可以从预先形成在基底的子集上的心轴上去除，例如使用光致抗蚀剂。 衬垫硬掩模可以在衬底的子集上的心轴上形成。 这种形成导致衬底的子集具有覆盖其上的心轴的衬垫硬掩模，并且具有覆盖其上的心轴的无定形碳层的衬底的其余部分。 该无定形碳层可以在基体的其余部分上从心轴上除去，允许在其中形成一组翅片，而无定形碳层保持该组翅片不会形成在其所覆盖的基底部分中。