公开(公告)号：US09496193B1

公开(公告)日：2016-11-15

申请号：US14858633

申请日：2015-09-18

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Gudrun Stranzl ,  Martin Zgaga ,  Martin Sporn ,  Tobias Schmidt

IPC: H01L23/04 ,  H01L21/48 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L23/12 ,  H01L23/00

CPC classification number: H01L24/32 ,  H01L21/4803 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3185 ,  H01L23/4827 ,  H01L24/05 ,  H01L24/26 ,  H01L24/29 ,  H01L24/83 ,  H01L24/94 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/04026 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/0556 ,  H01L2224/05644 ,  H01L2224/05687 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/291 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32245 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/0105 ,  H01L2924/053 ,  H01L2924/049

Abstract: A semiconductor chip includes a body having a frontside, a backside opposite the frontside, and sidewalls extending between the backside and frontside, at least a portion of each sidewall having a defined surface structure with hydrophobic characteristics to inhibit travel of a bonding material along the sidewalls during attachment of the semiconductor chip to a carrier with the bonding material.

Abstract translation: 半导体芯片包括具有前侧的主体，与前侧相对的后侧，以及在后侧和前侧之间延伸的侧壁，每个侧壁的至少一部分具有限定的具有疏水特性的表面结构，以阻止接合材料沿着侧壁移动 在使用所述接合材料将半导体芯片附接到载体的过程中。

公开(公告)号：US20150279740A1

公开(公告)日：2015-10-01

申请号：US14226666

申请日：2014-03-26

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Manfred Engelhardt ,  Johann Schmid ,  Gudrun Stranzl ,  Joachim Hirschler

IPC: H01L21/78 ,  H01L21/768

CPC classification number: H01L21/7806 ,  H01L21/02057 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/78 ,  H01L24/32 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2924/10157 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/00014 ,  H01L2924/00

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes attaching a substrate to a carrier using an adhesive component and forming a through trench through the substrate to expose the adhesive component. At least a portion of the adhesive component is etched and a metal layer is formed over sidewalls of the through trench.

Abstract translation: 根据本发明的实施例，一种形成半导体器件的方法包括：使用粘合剂组件将衬底附着到载体上，并通过衬底形成通孔以暴露粘合剂组分。 蚀刻粘合剂组分的至少一部分，并且在通孔的侧壁上形成金属层。

公开(公告)号：US20150206802A1

公开(公告)日：2015-07-23

申请号：US14158398

申请日：2014-01-17

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Gudrun Stranzl ,  Manfred Schneegans

IPC: H01L21/78 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L21/78 ,  B23H1/00 ,  B23H9/00 ,  H01L22/10 ,  H01L22/34 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of separating individual dies of a semiconductor wafer includes forming a metal layer on a first surface of a semiconductor wafer, the semiconductor wafer including a plurality of dies, separating the plurality of dies from one another, and electrical discharge machining the metal layer into individual segments each of which remains attached to one of the dies. A corresponding semiconductor die produced by such a method is also provided.

Abstract translation: 分离半导体晶片的各个管芯的方法包括在半导体晶片的第一表面上形成金属层，所述半导体晶片包括多个管芯，将多个管芯彼此分离，并将金属层进行放电加工成 各个片段保持附着于一个模具。 还提供了通过这种方法制造的相应的半导体管芯。

公开(公告)号：US11282805B2

公开(公告)日：2022-03-22

申请号：US16360570

申请日：2019-03-21

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Markus Menath ,  Gudrun Stranzl

IPC: H01L29/45 ,  H01L23/00 ,  H01L21/04 ,  H01L29/16

Abstract: A semiconductor device includes a silicon carbide layer, a metal carbide layer arranged over the silicon carbide layer, and a solder layer arranged over and in contact with the metal carbide layer.

公开(公告)号：US10157765B2

公开(公告)日：2018-12-18

申请号：US15359620

申请日：2016-11-23

Applicant: Infineon Technologies AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Rainer Leuschner ,  Bernhard Goller ,  Bernhard Boche ,  Manfred Engelhardt ,  Hermann Wendt ,  Bernd Noehammer ,  Karl Mayer ,  Michael Roesner ,  Monika Cornelia Voerckel

IPC: H01L23/498 ,  H01L21/683 ,  H01L21/283 ,  H01L21/78 ,  H01L21/033 ,  H01L21/285 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/768

Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.

公开(公告)号：US20170158493A1

公开(公告)日：2017-06-08

申请号：US15440962

申请日：2017-02-23

Applicant: Infineon Technologies AG

Inventor： Thomas Grille ,  Ursula Hedenig ,  Michael Roesner ,  Gudrun Stranzl ,  Martin Zgaga

IPC: B81B7/00 ,  B81C1/00 ,  B01D67/00

CPC classification number: B81B7/0061 ,  B01D67/0034 ,  B81B2201/0257 ,  B81B2201/10 ,  B81C1/00904 ,  B81C2201/0132 ,  Y10T428/24273

Abstract: A hole plate and a MEMS microphone arrangement are disclosed. In an embodiment a hole plate includes a substrate with a first main surface, a second main surface, and a lateral surface and a perforation structure formed within the substrate, the perforation structure having a plurality of through-holes through the substrate, wherein the through-holes and the lateral surface are a result of a simultaneous dry etching step.

公开(公告)号：US09673096B2

公开(公告)日：2017-06-06

申请号：US14541239

申请日：2014-11-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Joachim Hirschler ,  Michael Roesner ,  Markus Juch Heinrici ,  Gudrun Stranzl ,  Martin Mischitz ,  Martin Zgaga

IPC: H01L21/78 ,  H01L21/288 ,  H01L21/3213 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/288 ,  H01L21/3213 ,  H01L21/6835 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/94 ,  H01L24/95 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2224/03002 ,  H01L2224/03005 ,  H01L2224/03009 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/03505 ,  H01L2224/03848 ,  H01L2224/039 ,  H01L2224/05794 ,  H01L2224/05847 ,  H01L2224/06181 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2221/68381

Abstract: According to various embodiments, a method for processing a semiconductor substrate may include: covering a plurality of die regions of the semiconductor substrate with a metal; forming a plurality of dies from the semiconductor substrate, wherein each die of the plurality of dies is covered with the metal; and, subsequently, annealing the metal covering at least one die of the plurality of dies.

公开(公告)号：US09640419B2

公开(公告)日：2017-05-02

申请号：US14451043

申请日：2014-08-04

Applicant: Infineon Technologies AG

Inventor： Manfred Schneegans ,  Martin Mischitz ,  Michael Roesner ,  Michael Pinczolits

IPC: H01L21/683 ,  H01L21/02 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L21/6836 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/49551 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/28 ,  H01L24/32 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2224/03002 ,  H01L2224/0346 ,  H01L2224/03602 ,  H01L2224/0391 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/03

Abstract: In accordance with an alternative embodiment of the present invention, a method for forming a semiconductor device includes applying a paste over a semiconductor substrate, and forming a ceramic carrier by solidifying the paste. The semiconductor substrate is thinned using the ceramic carrier as a carrier.

公开(公告)号：US09610543B2

公开(公告)日：2017-04-04

申请号：US14170187

申请日：2014-01-31

Applicant: Infineon Technologies AG

Inventor： Thomas Grille ,  Ursula Hedenig ,  Michael Roesner ,  Gudrun Stranzl ,  Martin Zgaga

IPC: H01L21/00 ,  B01D67/00 ,  B81C1/00

CPC classification number: B81B7/0061 ,  B01D67/0034 ,  B81B2201/0257 ,  B81B2201/10 ,  B81C1/00904 ,  B81C2201/0132 ,  Y10T428/24273

Abstract: A method for structuring a substrate and a structured substrate are disclosed. In an embodiment a method includes providing a substrate with a first main surface and a second main surface, wherein the substrate is fixed to a carrier arrangement at the second main surface, performing a photolithography step at the first main surface of the substrate to mark a plurality of sites at the first main surface, the plurality of sites corresponding to future perforation structures and future kerf regions for a plurality of future individual semiconductor chips to be obtained from the substrate, and plasma etching the substrate at the plurality of sites until the carrier arrangement is reached, thus creating the perforation structures within the plurality of individual semiconductor chips and simultaneously separating the individual semiconductor chips along the kerf regions.

公开(公告)号：US20160379884A1

公开(公告)日：2016-12-29

申请号：US14751035

申请日：2015-06-25

Applicant: Infineon Technologies AG

Inventor： Joerg Ortner ,  Michael Roesner ,  Gudrun Stranzl ,  Rudolf Rothmaler

IPC: H01L21/78 ,  H01L21/308 ,  G03F1/38 ,  H01L21/3065

CPC classification number: H01L21/78 ,  G03F1/38 ,  H01L21/3065 ,  H01L21/3083

Abstract: A method of dicing a wafer includes providing a wafer and etching the wafer to singulate die between kerf line segments defined within an interior region of the wafer and to singulate a plurality of wafer edge areas between the kerf line segments and a circumferential edge of the wafer. Each one of the plurality of wafer edge areas is singulated by kerf lines that each extend between one of two endpoints of one of the kerf line segments and the circumferential edge of the wafer.

Abstract translation: 切割晶片的方法包括提供晶片并蚀刻晶片以在限定在晶片的内部区域内的切口线段之间划分管芯并且在切口线段与晶片的周边边缘之间划分多个晶片边缘区域 。 多个晶片边缘区域中的每一个由切割线分割，每条切割线各自在切割线段之一的两个端点之一和晶片的周边边缘之间延伸。