公开(公告)号：US20240272547A1

公开(公告)日：2024-08-15

申请号：US18620187

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： Charles Cameron Mokhtarzadeh ,  Sanjana Vijay Karpe ,  Scott B. Clendenning ,  James Munro Blackwell ,  Lauren Elizabeth Doyle ,  Brandon Jay Holybee

IPC: G03F7/004 ,  C23C16/40 ,  C23C16/455 ,  C23C16/56 ,  G03F7/00 ,  G03F7/16 ,  G03F7/20 ,  H01L21/033

CPC classification number: G03F7/0042 ,  C23C16/407 ,  C23C16/45534 ,  C23C16/45553 ,  C23C16/56 ,  G03F7/161 ,  G03F7/162 ,  G03F7/2002 ,  G03F7/70033 ,  H01L21/0337

Abstract: Tin carboxylate precursors for metal oxide resist layers and related methods are disclosed herein. An example method of fabricating a semiconductor device disclosed herein includes synthesizing a precursor including tin, depositing a metal oxide resist layer on a base material by applying the precursor, the metal oxide resist layer including tin-6 clusters, and patterning the metal oxide resist layer.

公开(公告)号：US20240222485A1

公开(公告)日：2024-07-04

申请号：US18091209

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Tristan Tronic ,  Chelsey Dorow ,  Kevin O?Brien ,  Uygar Avci ,  Carl H. Naylor ,  Chia-Ching Lin ,  Dominique Adams ,  Matthew Metz ,  Ande Kitamura ,  Scott B. Clendenning

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/26 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/26 ,  H01L29/42392 ,  H01L29/66969

Abstract: A transistor structure includes a stack of nanoribbons coupling source and drain terminals. The nanoribbons may each include a pair of crystalline interface layers and a channel layer between the interface layers. The channel layers may be a molecular monolayer, including a metal and a chalcogen, with a thickness of less than 1 nm. The channel layers may be substantially monocrystalline, and the interface layers may be lattice matched to the channel layers. The channel layers may be epitaxially grown over the lattice-matched interface layers. The crystalline interface layers may be grown over sacrificial layers when forming the stack of nanoribbons.

公开(公告)号：US11901404B2

公开(公告)日：2024-02-13

申请号：US17578043

申请日：2022-01-18

Applicant: Intel Corporation

Inventor： Sudipto Naskar ,  Manish Chandhok ,  Abhishek A. Sharma ,  Roman Caudillo ,  Scott B. Clendenning ,  Cheyun Lin

IPC: H01L21/00 ,  H01L49/02 ,  H10B12/00

CPC classification number: H01L28/87 ,  H10B12/033 ,  H10B12/31

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11791375B2

公开(公告)日：2023-10-17

申请号：US17578839

申请日：2022-01-19

Applicant: Intel Corporation

Inventor： Sudipto Naskar ,  Manish Chandhok ,  Abhishek A. Sharma ,  Roman Caudillo ,  Scott B. Clendenning ,  Cheyun Lin

IPC: H01L21/00 ,  H01L49/02 ,  H10B12/00

CPC classification number: H01L28/87 ,  H10B12/033 ,  H10B12/31

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11532724B2

公开(公告)日：2022-12-20

申请号：US17154755

申请日：2021-01-21

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Szuya S. Liao ,  Florian Gstrein ,  Rami Hourani ,  Patricio E. Romero ,  Grant M. Kloster ,  Martin M. Mitan

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/304 ,  H01L29/161 ,  H01L29/06 ,  H01L21/265 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775 ,  H01L21/28 ,  H01L29/49 ,  H01L21/266

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

公开(公告)号：US20220199620A1

公开(公告)日：2022-06-23

申请号：US17127280

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Nicole Thomas ,  Eric Mattson ,  Sudarat Lee ,  Scott B. Clendenning ,  Tobias Brown-Heft ,  I-Cheng Tung ,  Thoe Michaelos ,  Gilbert Dewey ,  Charles Kuo ,  Matthew Metz ,  Marko Radosavljevic ,  Charles Mokhtarzadeh

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

Abstract: Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (Vt). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vt within the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.

公开(公告)号：US11217456B2

公开(公告)日：2022-01-04

申请号：US16955012

申请日：2018-03-26

Applicant: Intel Corporation

Inventor： James M. Blackwell ,  Scott B. Clendenning ,  Cen Tan ,  Marie Krysak

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: Selective etching and controlled atomic layer etching of transition metal oxide films for device fabrication, and the resulting devices, are described. In an example, method of dry etching a film includes forming a transition metal oxide film having a latent pore-forming material therein. The method also includes removing a surface portion of the latent pore-forming material of the transition metal oxide film to form a porous region of the transition metal oxide film. The method also includes removing the porous region of the transition metal oxide film.

公开(公告)号：US10777366B2

公开(公告)日：2020-09-15

申请号：US15936427

申请日：2018-03-26

Applicant: Intel Corporation

Inventor： Donald S. Gardner ,  Zhaohui Chen ,  Wei C. Jin ,  Scott B. Clendenning ,  Eric C. Hannah ,  Tomm V. Aldridge ,  John L. Gustafson

IPC: H01G11/26 ,  H01G11/86 ,  H01G11/58 ,  H01G11/14 ,  H01G11/30

Abstract: Methods of increasing an energy density of an energy storage device involve increasing the capacitance of the energy storage device by depositing a material into a porous structure of the energy storage device using an atomic layer deposition process, by performing a procedure designed to increase a distance to which an electrolyte penetrates within channels of the porous structure, or by placing a dielectric material into the porous structure. Another method involves annealing the energy storage device in order to cause an electrically conductive substance to diffuse to a surface of the structure and form an electrically conductive layer thereon. Another method of increasing energy density involves increasing the breakdown voltage and another method involves forming a pseudocapacitor. A method of increasing an achievable power output of an energy storage device involves depositing an electrically conductive material into the porous structure.

公开(公告)号：US10756215B2

公开(公告)日：2020-08-25

申请号：US16271226

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Grant Kloster ,  Scott B. Clendenning ,  Rami Hourani ,  Szuya S. Liao ,  Patricio E. Romero ,  Florian Gstrein

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L29/06 ,  H01L29/786 ,  H01L21/31 ,  H01L23/498 ,  H01L21/32 ,  H01L29/423

Abstract: Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.

公开(公告)号：US20190189505A1

公开(公告)日：2019-06-20

申请号：US16326135

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Scott B. Clendenning ,  Florian Gstrein

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/28556 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76846 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53276 ,  H01L23/53295

Abstract: Disclosed are electronic device assemblies, computing devices, and related methods. An electronic device assembly or a computing device includes an interlayer dielectric region between a first region and a second region, a conductive interlayer structure formed through the interlayer dielectric region, and a barrier region formed around the conductive interlayer structure. The conductive interlayer structure includes a composition of Ml-Alm—X1n—X2p—Cq—Or, wherein M comprises a metal selected from one or more of titanium, zirconium, hafnium, tantalum, niobium and vanadium; C comprises carbon; O comprises oxygen; X1 comprises gallium; X2 comprises indium; and l, m, n, p, q and r represent an atomic percent of an element in the barrier region that can be 0 percent, but n and p cannot both be 0 percent. A method includes forming the barrier region within a passage through the interlayer dielectric region.