公开(公告)号：US11915926B2

公开(公告)日：2024-02-27

申请号：US17485659

申请日：2021-09-27

Applicant: International Business Machines Corporation

Inventor： Leonidas Ernesto Ocola ,  Eric A. Joseph ,  Hiroyuki Miyazoe ,  Takashi Ando ,  Damon Brooks Farmer

IPC: H01L21/02 ,  H01L29/40 ,  C23C16/02 ,  C23C16/04 ,  C23C16/40 ,  C23C16/455

CPC classification number: H01L21/02203 ,  C23C16/0245 ,  C23C16/045 ,  C23C16/403 ,  C23C16/45525 ,  H01L21/02178 ,  H01L21/02181 ,  H01L29/408

Abstract: A porous thin film includes a framework that includes a plurality of pores. The pores extend from an opening located at an upper surface of the framework to a bottom surface contained in the framework. A pore-coating film is formed on sidewalls and the bottom surface of the pores.

公开(公告)号：US10607899B2

公开(公告)日：2020-03-31

申请号：US15397141

申请日：2017-01-03

Applicant: International Business Machines Corporation

Inventor： Shawn A. Adderly ,  Jeffrey P. Gambino ,  Eric A. Joseph ,  Anthony C. Speranza

IPC: H01L21/67 ,  H01L21/66 ,  H01L21/768 ,  H01J37/32 ,  H05H1/24 ,  C23C16/04 ,  C23C16/513 ,  G01N23/2252 ,  H01L21/48

Abstract: An apparatus for and methods of repairing and manufacturing integrated circuits using the apparatus. The apparatus, comprising: a vacuum chamber containing: a movable stage configured to hold a substrate; an inspection and analysis probe; a heat source; a gas injector; and a gas manifold connecting multiple gas sources to the gas injector.

公开(公告)号：US10529633B2

公开(公告)日：2020-01-07

申请号：US15833866

申请日：2017-12-06

Applicant: International Business Machines Corporation

Inventor： Sebastian U. Engelmann ,  Eric A. Joseph

IPC: H01L21/308 ,  H01L21/66 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/265

Abstract: A method of forming integrated circuit (IC) chips. After masking a layer of a material to be etched, the layer is subjected to an atomic layer etch (ALE). During the ALE, etch effluent is measured with a calorimetric probe. The calorimetric probe results reflect a species of particles resulting from etching the material. The measured etch results are checked until the results indicate the particle content is below a threshold value. When the content is below the threshold ALE is complete and IC chip fabrication continues normally.

公开(公告)号：US10388857B2

公开(公告)日：2019-08-20

申请号：US15184109

申请日：2016-06-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony J. Annunziata ,  Armand A. Galan ,  Steve Holmes ,  Eric A. Joseph ,  Gen P. Lauer ,  Qinghuang Lin ,  Nathan P. Marchack

IPC: H01L43/10 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  G03F7/20 ,  H01L27/22

Abstract: A magnetoresistive memory cell includes a magnetic tunnel junction pillar having a circular cross section. The pillar has a pinned magnetic layer, a tunnel barrier layer, and a free magnetic layer. A first conductive contact is disposed above the magnetic tunnel junction pillar. A second conductive contact is disposed below the magnetic tunnel junction pillar.

公开(公告)号：US10167443B2

公开(公告)日：2019-01-01

申请号：US15334863

申请日：2016-10-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Zeon Corporation

Inventor： Robert L. Bruce ,  Sebastian U. Engelmann ,  Eric A. Joseph ,  Mahmoud Khojasteh ,  Masahiro Nakamura ,  Satyavolu S. Papa Rao ,  Bang N. To ,  George G. Totir ,  Yu Zhu

IPC: C11D3/04 ,  C11D7/10 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  C11D11/00 ,  H01L29/66 ,  H01L21/3065

Abstract: A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution removes an etch residue that includes a majority of hydrocarbons and at least one element selected from the group consisting of carbon, oxygen, fluorine, nitrogen and silicon. In one example, the aqueous solution may be cerium ammonium nitrate (Ce(NH4)(NO3)),(CAN).

公开(公告)号：US20180122649A1

公开(公告)日：2018-05-03

申请号：US15847369

申请日：2017-12-19

Applicant: International Business Machines Corporation ,  Zeon Corporation

Inventor： Robert L. Bruce ,  Eric A. Joseph ,  Joe Lee ,  Takefumi Suzuki

IPC: H01L21/311 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L21/31116 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5329

Abstract: In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.

公开(公告)号：US09799519B1

公开(公告)日：2017-10-24

申请号：US15192196

申请日：2016-06-24

Applicant: International Business Machines Corporation

Inventor： Eric A. Joseph ,  Hiroyuki Miyazoe

IPC: H01L21/768 ,  H01L21/263 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/2633 ,  H01L21/76829 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76885 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329

Abstract: A dielectric layer is formed on a silicon substrate. A liner layer is formed on the dielectric layer. A conductive metal layer is formed on the liner layer. A first sputter etching operation is performed on the conductive metal layer, wherein the first sputter etching operation uses a first type of etch chemistry configured to subtractively pattern the conductive metal layer for a first etching time period resulting in the remaining conductive metal layer having respective sidewalls that are not substantially vertical. A second sputter etching operation is performed on the remaining conductive metal layer, wherein the second sputter etching operation uses a second type of etch chemistry configured to further subtractively pattern the remaining conductive metal layer for a second etching time period resulting in the remaining conductive metal layer having respective sidewalls that are substantially vertical. The conductive metal layer remaining after the second sputter etching operation comprises a metal interconnect.

公开(公告)号：US09786550B2

公开(公告)日：2017-10-10

申请号：US14749811

申请日：2015-06-25

Applicant: International Business Machines Corporation

Inventor： Stephen M. Gates ,  Gregory M. Fritz ,  Eric A. Joseph ,  Terry A. Spooner

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76814 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76888 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53266

Abstract: A semiconductor device and a method of fabricating a contact to interface with an interconnect in a semiconductor device are described. The device includes a dielectric layer formed on a semiconductor layer, and a contact fabricated in a via formed within the dielectric layer. An interconnect formed above the contact interfaces with an exposed surface of the contact opposite a surface closest to the semiconductor layer. The contact includes a contact material in a first portion of the contact and an interface metal in a second portion of the contact.

公开(公告)号：US20170194161A1

公开(公告)日：2017-07-06

申请号：US14985951

申请日：2015-12-31

Applicant: International Business Machines Corporation

Inventor： Markus Brink ,  Sebastian U. Engelmann ,  Eric A. Joseph ,  Hiroyuki Miyazoe

IPC: H01L21/311 ,  H01L21/02

CPC classification number: H01L21/31116 ,  H01L21/02321 ,  H01L21/31144

Abstract: A method of etching a pattern into a dielectric layer is provided. An organic planarization layer having a pattern is provided atop a dielectric layer. A cyclic fluorocarbon deposition step and plasma step is performed to etch the pattern into the dielectric layer. The energy for the plasma step is kept below the etch threshold of the dielectric layer.

公开(公告)号：US20170154815A1

公开(公告)日：2017-06-01

申请号：US15430672

申请日：2017-02-13

Applicant: International Business Machines Corporation

Inventor： Robert L. Bruce ,  Gregory M. Fritz ,  Eric A. Joseph ,  Hiroyuki Miyazoe

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L24/05 ,  H01L2224/05025 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147

Abstract: In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.