公开(公告)号：US09208938B2

公开(公告)日：2015-12-08

申请号：US14044269

申请日：2013-10-02

Applicant: International Business Machines Corporation

Inventor： Hanyi Ding ,  Anthony K. Stamper

IPC: H01F5/00 ,  H01F27/30 ,  H01L27/08 ,  H01L21/76 ,  H01F27/28 ,  H01F17/00

CPC classification number: H01F27/006 ,  H01F17/0013 ,  H01F27/2804 ,  H01F2017/004 ,  H01F2027/2819

Abstract: Various embodiments include inductor structures including at least one air gap for reducing capacitance between windings in the inductor structure. One embodiment includes an inductor structure having: a substrate; an insulation layer overlying the substrate; a conductive winding overlying the substrate within the insulation layer, the conductive winding wrapped around itself to form a plurality of turns substantially concentric about a central axis; an insulating structural support containing an air gap between the conductive winding and the insulation layer, the insulating structural support at least one of under, over or surrounding the plurality of turns of the conductive winding or between adjacent turns in the conductive winding; and at least one insulation pocket located radially inside a radially innermost turn in the plurality of turns with respect to the central axis.

Abstract translation: 各种实施例包括电感器结构，其包括用于减小电感器结构中的绕组之间的电容的至少一个气隙。 一个实施例包括电感结构，其具有：基板; 覆盖衬底的绝缘层; 导电绕组，覆盖绝缘层内的衬底，导电绕组缠绕在其周围以形成基本上围绕中心轴同心的多个匝; 所述绝缘结构支撑体包含所述导电绕组和所述绝缘层之间的空气间隙，所述绝缘结构支撑件处于所述导电绕组的多匝或所述导电绕组的相邻匝之间的下方，上方或周围中的至少一个; 以及位于所述多个匝中相对于所述中心轴线的径向最内侧的径向内侧的至少一个绝缘袋。

公开(公告)号：US09171121B2

公开(公告)日：2015-10-27

申请号：US13763136

申请日：2013-02-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hanyi Ding ,  Alvin J. Joseph ,  Wayne H. Woods, Jr.

IPC: H01L21/20 ,  G06F17/50 ,  H01L23/48 ,  H01P5/16 ,  H01P11/00

CPC classification number: G06F17/5077 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P5/16 ,  H01P11/007 ,  H01L2924/00

Abstract: A method, structure, and design structure for a through-silicon-via Wilkinson power divider. A method includes: forming an input on a first side of a substrate; forming a first leg comprising a first through-silicon-via formed in the substrate, wherein the first leg electrically connects the input and a first output; forming a second leg comprising a second through-silicon-via formed in the substrate, wherein the second leg electrically connects the input and a second output, and forming a resistor electrically connected between the first output and the second output.

Abstract translation: 一种通过硅通孔威尔金森功率分配器的方法，结构和设计结构。 一种方法包括：在基板的第一侧上形成输入; 形成包括在所述基板中形成的第一穿通硅通孔的第一支脚，其中所述第一支路电连接所述输入端和第一输出端; 形成包括形成在所述基板中的第二通硅通孔的第二支脚，其中所述第二支脚电连接所述输入端和第二输出端，以及形成电连接在所述第一输出端和所述第二输出端之间的电阻器。

公开(公告)号：US20150091686A1

公开(公告)日：2015-04-02

申请号：US14044269

申请日：2013-10-02

Applicant: International Business Machines Corporation

Inventor： Hanyi Ding ,  Anthony K. Stamper

IPC: H01F27/28

CPC classification number: H01F27/006 ,  H01F17/0013 ,  H01F27/2804 ,  H01F2017/004 ,  H01F2027/2819

Abstract: Various embodiments include inductor structures including at least one air gap for reducing capacitance between windings in the inductor structure. One embodiment includes an inductor structure having: a substrate; an insulation layer overlying the substrate; a conductive winding overlying the substrate within the insulation layer, the conductive winding wrapped around itself to form a plurality of turns substantially concentric about a central axis; an insulating structural support containing an air gap between the conductive winding and the insulation layer, the insulating structural support at least one of under, over or surrounding the plurality of turns of the conductive winding or between adjacent turns in the conductive winding; and at least one insulation pocket located radially inside a radially innermost turn in the plurality of turns with respect to the central axis.

Abstract translation: 各种实施例包括电感器结构，其包括用于减小电感器结构中的绕组之间的电容的至少一个气隙。 一个实施例包括电感结构，其具有：基板; 覆盖衬底的绝缘层; 导电绕组，覆盖绝缘层内的衬底，导电绕组缠绕在其周围以形成基本上围绕中心轴同心的多个匝; 所述绝缘结构支撑体包含所述导电绕组和所述绝缘层之间的空气间隙，所述绝缘结构支撑件在所述导电绕组的所述多匝或所述导电绕组的相邻匝之间的下方，上方或周围中的至少一个上; 以及位于所述多个匝中相对于所述中心轴线的径向最内侧的径向内侧的至少一个绝缘袋。

公开(公告)号：US20150024693A1

公开(公告)日：2015-01-22

申请号：US13945969

申请日：2013-07-19

Applicant: International Business Machines Corporation

Inventor： Donald J. Cook ,  Hanyi Ding ,  Xuefeng Liu ,  Randy L. Wolf

IPC: H04B17/00

CPC classification number: H04B17/19 ,  G01R31/2822 ,  G01R31/2856 ,  G01R31/2879 ,  G06K19/07728 ,  H01L22/34

Abstract: Disclosed are test structures for radio frequency (RF) power stress and characterization. Each test structure incorporates a single device and is selectively operated in either a stress mode, during which the device is stressed under RF power, or in an analysis mode, during which the impact of the applied stress on the performance of the device is characterized. During the stress mode, an input RF power signal is applied to the device through an RF signal input port and an output RF power signal is captured from the device at an RF signal output port. Depending upon the impedance value of the device at issue, the RF signal input port and the RF signal output port are connected to either the same terminal or opposing terminals and the need for impedance tuning is avoided. Also disclosed are test systems and methods for selectively controlling operation of such a test structure.

Abstract translation: 公开了用于射频（RF）功率应力和表征的测试结构。 每个测试结构包括单个设备，并且在应力模式中选择性地操作，在该模式期间，器件在RF功率下受到压力，或者在分析模式下，其中施加的应力对器件的性能的影响被表征。 在应力模式期间，通过RF信号输入端口向设备施加输入RF功率信号，并且在RF信号输出端口处从设备捕获输出RF功率信号。 根据所讨论的器件的阻抗值，RF信号输入端口和RF信号输出端口连接到相同的端子或相对的端子，并且避免了阻抗调谐的需要。 还公开了用于选择性地控制这种测试结构的操作的测试系统和方法。

公开(公告)号：US08907470B2

公开(公告)日：2014-12-09

申请号：US13772715

申请日：2013-02-21

Applicant: International Business Machines Corporation

Inventor： Hanyi Ding ,  Richard S. Graf ,  Gary R. Hill ,  Wayne H. Woods, Jr.

IPC: H01L23/492 ,  H01L21/66 ,  H01L23/498

CPC classification number: H01L24/17 ,  H01L22/12 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5225 ,  H01L23/66 ,  H01L24/09 ,  H01L2224/0401 ,  H01L2224/16055 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1713 ,  H01L2924/0002 ,  H01L2924/1532 ,  H01L2924/2076 ,  H01L2924/00

Abstract: Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad.

Abstract translation: 各种实施例包括晶片级芯片级封装（WLCSP）结构和调谐这种结构的方法。 在一些实施例中，WLCSP结构包括：印刷电路板（PCB）迹线连接，其包括与PCB接地平面连接的至少一个PCB接地连接; 一组接地焊球，每个接触印刷电路板跟踪连接; 与所述一组接地焊球中的所述接地焊球接触的一组芯片焊盘; 连接该组芯片焊盘的芯片接地平面; 以及插入在所述一组接地焊球中的两个之间的信号互连，所述信号互连包括：与所述PCB接地平面电隔离的信号迹线连接; 信号球接触信号PCB跟踪连接; 接触信号球的芯片焊盘和与芯片焊盘接触的芯片上的信号迹线连接。

公开(公告)号：US20140332973A1

公开(公告)日：2014-11-13

申请号：US13889374

申请日：2013-05-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hanyi Ding ,  J. Edwin Hostetter, JR. ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC: H01L21/66

CPC classification number: H01L22/26 ,  H01L21/304 ,  H01L22/14 ,  H01L22/34

Abstract: A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.

Abstract translation: 公开了一种通过硅通孔（TSV）电容测试结构和基于电容确定TSV深度的方法。 TSV电容测试结构由均匀间隔的多个TSV条形成。 第一组电杆电连接以形成第一电容器节点，并且第二组电杆电连接以形成第二电容器节点。 测量电容，并在背面变薄之前计算TSV深度。 然后计算的TSV深度可以被馈送到下游研磨和/或抛光工具以控制背面变薄处理，使得半导体晶片变薄使得背面与TSV齐平。

公开(公告)号：US08789003B1

公开(公告)日：2014-07-22

申请号：US13867422

申请日：2013-04-22

Applicant: International Business Machines Corporation

Inventor： Hanyi Ding ,  Alberto Valdes Garcia ,  Wayne H. Woods, Jr.

IPC: G06F11/22 ,  G06F17/50 ,  G06F9/455

CPC classification number: G06F11/22 ,  G06F17/50 ,  G06F17/5063

Abstract: Methods for creating a tunable phase shifter include setting physical dimension limits for the tunable phase shifter; determining electrical parameters for the tunable phase shifter, including a characteristic impedance limit and a maximum inductance tuning range, based on the physical dimension limits using a processor; and determining physical dimensions for an inductance tuning transistor and a capacitor tuning transistor, such that a characteristic impedance range is minimized.

Abstract translation: 用于创建可调谐移相器的方法包括设置可调谐移相器的物理尺寸限制; 基于使用处理器的物理尺寸限制，确定可调谐移相器的电参数，包括特征阻抗极限和最大电感调谐范围; 以及确定电感调谐晶体管和电容调谐晶体管的物理尺寸，使得特性阻抗范围最小化。

公开(公告)号：US20130189827A1

公开(公告)日：2013-07-25

申请号：US13665976

申请日：2012-11-01

Applicant: International Business Machines Corporation

Inventor： Hanyi Ding ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/481 ,  H01L24/05 ,  H01L24/10 ,  H01L24/12 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/2518 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The structure includes, a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of to the bottom surface of the substrate, the at least one electrically conductive via electrically isolated from the substrate.

Abstract translation: 用于通过晶片通孔形成和结构的方法，所述晶片通孔和通过晶片通孔形成的信号传输线。 该结构包括：具有顶表面和相对底表面的半导体衬底; 以及贯穿晶片通孔的阵列，其包括至少一个导电的通过晶片通孔和至少一个非导电的通过晶片通孔，每个通过晶片通孔的通过晶片通孔的阵列从顶表面延伸到底表面 所述衬底，所述至少一个导电通孔与所述衬底电隔离。

公开(公告)号：US20130125079A1

公开(公告)日：2013-05-16

申请号：US13738367

申请日：2013-01-10

Applicant: International Business Machines Corporation

Inventor： Hanyi Ding ,  Wayne H. Woods, JR.

IPC: G06F17/50

CPC classification number: H01L28/10 ,  G06F17/5068 ,  G06F17/5077 ,  H01L21/31053 ,  H01L21/76808 ,  H01L21/76826 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/08 ,  H01L29/432 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.

公开(公告)号：US09813264B2

公开(公告)日：2017-11-07

申请号：US14835286

申请日：2015-08-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hanyi Ding ,  Alberto Valdes Garcia ,  Wayne H. Woods, Jr.

IPC: H04L25/02 ,  H01P1/18 ,  H01R43/00 ,  H03K17/687 ,  G06F17/50

CPC classification number: H04L25/0278 ,  G06F17/50 ,  H01P1/182 ,  H01P1/184 ,  H01R43/00 ,  H03K17/687 ,  H04L25/0272

Abstract: Tunable phase shifters and methods for using the same include a signal line; one or more grounding lines; one or more crossing lines below the signal line in proximity to the signal line and substantially perpendicular to a longitudinal direction of the signal line, where the crossing lines conform to the shape of the signal line along at least three surfaces of the signal line and where the crossing lines have a tunable capacitance; and an inductance return line below the crossing lines substantially parallel to the longitudinal direction of the signal line, where the inductance return line provides a tunable inductance.