利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

70 条记录 (耗时 0.062 秒)

    Method of fabricating metal lines in a semiconductor device
    31.
    发明授权
    Method of fabricating metal lines in a semiconductor device 有权
    在半导体器件中制造金属线的方法

    公开(公告)号：US06787468B2

    公开(公告)日：2004-09-07

    申请号：US10035257

    申请日：2002-01-04

    申请人： Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Gil-Heyun Choi

    发明人： Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Gil-Heyun Choi

    IPC分类号： H01L2144

    CPC分类号： H01L21/76844 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76882 ,  H01L2221/1089

    摘要： A method of fabricating a semiconductor device having a recess region in an insulation layer on a silicon substrate, comprising the steps of depositing a barrier metal over the entire surface of the insulation layer including the substrate surface in the recess region, depositing selectively an anti-nucleation layer on the barrier metal except in the recess region, depositing a CVD-Al layer on the barrier metal in the recess region, depositing a metal or a metal alloy inhibiting aluminum migration on the anti-nucleation layer and the barrier metal except in the recess region, and depositing a PVD-Al layer and re-flowing the PVD-Al layer, for improving the quality of aluminum grooves. The present method inhibits PVD-Al migration and grain growth, which results in preventing abnormal patterning in the semiconductor device.

    摘要翻译： 一种制造在硅衬底上的绝缘层中具有凹陷区域的半导体器件的方法，包括以下步骤：在包括凹陷区域中的衬底表面的绝缘层的整个表面上沉积阻挡金属， 在凹陷区域之外的阻挡金属上的成核层，在凹陷区域中的阻挡金属上沉积CVD-Al层，在抗成核层和除了在...中形成的阻挡金属之外沉积抑制铝迁移的金属或金属合金 并且沉积PVD-Al层并再次流动PVD-Al层，以改善铝槽的质量。 本方法抑制PVD-Al迁移和晶粒生长，这导致防止半导体器件中的异常图案化。

    Semiconductor device conductive pattern structures and methods of manufacturing the same
    32.
    发明授权
    Semiconductor device conductive pattern structures and methods of manufacturing the same 有权
    半导体器件导电图案结构及其制造方法

    公开(公告)号：US08592979B2

    公开(公告)日：2013-11-26

    申请号：US13440123

    申请日：2012-04-05

    申请人： Hei-Seung Kim ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee

    发明人： Hei-Seung Kim ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L27/11524 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76877 ,  H01L23/528 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A conductive pattern structure includes a first insulating interlayer on a substrate, metal wiring on the first insulating interlayer, a second insulating interlayer on the metal wiring, and first and second metal contacts extending through the second insulating interlayer. The first metal contacts contact the metal wiring in a cell region and the second metal contact contacts the metal wiring in a peripheral region. A third insulating interlayer is disposed on the second insulating interlayer. Conductive segments extend through the third insulating interlayer in the cell region and contact the first metal contacts. Another conductive segment extends through the third insulating interlayer in the peripheral region and contacts the second metal contact. The structure facilitates the forming of uniformly thick wiring in the cell region using an electroplating process.

    摘要翻译： 导电图案结构包括在基板上的第一绝缘中间层，第一绝缘中间层上的金属布线，金属布线上的第二绝缘中间层以及延伸穿过第二绝缘夹层的第一和第二金属触点。 第一金属触点与单元区域中的金属布线接触，并且第二金属触点与外围区域中的金属布线接触。 第三绝缘中间层设置在第二绝缘中间层上。 导电部分延伸通过电池区域中的第三绝缘中间层并与第一金属触点接触。 另一个导电段延伸穿过周边区域中的第三绝缘中间层并接触第二金属接触。 该结构有助于使用电镀工艺在电池区域中形成均匀厚的布线。

    Semiconductor device and methods of forming the same
    34.
    发明授权
    Semiconductor device and methods of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：US07807571B2

    公开(公告)日：2010-10-05

    申请号：US11892089

    申请日：2007-08-20

    申请人： Kyung-In Choi ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hyun-Bae Lee

    发明人： Kyung-In Choi ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hyun-Bae Lee

    IPC分类号： H01L21/44 ,  H01L23/52

    CPC分类号： H01L21/76868 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An example embodiment provides a method of forming a conductive pattern in a semiconductor device. The method includes forming one or more dielectric layers over a first conductive pattern formed on a substrate; forming an opening in the one or more dielectric layers to expose a portion of the first conductive pattern, forming a growth promoting layer over the exposed portion of the first conductive pattern and the one or more dielectric layers, forming a growth inhibiting layer over a portion of the growth promoting layer, and forming the second conductive layer in the opening.

    摘要翻译： 示例性实施例提供了在半导体器件中形成导电图案的方法。 该方法包括在形成在衬底上的第一导电图案上形成一个或多个电介质层; 在所述一个或多个电介质层中形成开口以暴露所述第一导电图案的一部分，在所述第一导电图案和所述一个或多个介电层的暴露部分上形成增长促进层，在所述第一导电图案的一部分上形成生长抑制层 的生长促进层，并且在开口中形成第二导电层。

    Methods of Fabricating Semiconductor Devices Having Conductive Wirings and Related Flash Memory Devices
    35.
    发明申请
    Methods of Fabricating Semiconductor Devices Having Conductive Wirings and Related Flash Memory Devices 审中-公开
    制造具有导电布线和相关闪存设备的半导体器件的方法

    公开(公告)号：US20100237504A1

    公开(公告)日：2010-09-23

    申请号：US12789982

    申请日：2010-05-28

    申请人： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Hyun Park ,  Kyung-In Choi ,  Hyun-Bae Lee

    发明人： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Hyun Park ,  Kyung-In Choi ,  Hyun-Bae Lee

    IPC分类号： H01L23/522 ,  H01L21/768

    CPC分类号： H01L27/115 ,  H01J2237/0812 ,  H01L27/11521 ,  H01L27/11524

    摘要： A conductive wiring for a semiconductor device is provided including a semiconductor substrate and a plurality of lower conductive structures on the semiconductor substrate. An insulating layer is provided that electrically insulates the plurality of lower conductive structures from one another. A first insulation interlayer pattern is provided on the insulation layer. The first insulation interlayer pattern includes a contact plug that contacts the substrate through the insulation layer. An etch-stop layer is provided on the contact plug and the first insulation interlayer pattern. A second insulation interlayer pattern is provided on the etch-stop layer. The second insulation interlayer pattern includes a conductive line that is electrically connected to the contact plug. Related methods and flash memory devices are also provided.

    摘要翻译： 在半导体衬底上设置有半导体衬底和多个下导电结构的半导体器件用导电布线。 提供了使多个下导电结构彼此电绝缘的绝缘层。 在绝缘层上设置第一绝缘夹层图案。 第一绝缘层间图案包括通过绝缘层接触衬底的接触插塞。 在接触插塞和第一绝缘层间图案上设置有蚀刻停止层。 在蚀刻停止层上设置第二绝缘层间图案。 第二绝缘层间图案包括电连接到接触插塞的导线。 还提供了相关方法和闪存设备。

    METHODS OF FORMING FILMS OF A SEMICONDUCTOR DEVICE
    37.
    发明申请
    METHODS OF FORMING FILMS OF A SEMICONDUCTOR DEVICE 审中-公开
    形成半导体器件膜的方法

    公开(公告)号：US20080318421A1

    公开(公告)日：2008-12-25

    申请号：US12137059

    申请日：2008-06-11

    申请人： Jong-Ho Yun ,  Gil-Heyun Choi ,  Jong-Myeong Lee

    发明人： Jong-Ho Yun ,  Gil-Heyun Choi ,  Jong-Myeong Lee

    IPC分类号： H01L21/3205 ,  H01L21/3065

    CPC分类号： H01L21/288 ,  C23C18/1658 ,  C23C18/1689 ,  C23C18/1879 ,  C23C18/30 ,  C23C18/31 ,  H01L21/76849

    摘要： There is provided a method of forming a film of a semiconductor device. The method includes a step of adsorbing a liquefied metal ion source on the substrate; rinsing the substrate to remove any liquefied metal ion source that is not adsorbed to the substrate; depositing a metal layer on the substrate by reducing the liquefied metal ion source that is adsorbed on the substrate with a liquefied reducing agent; and rinsing the substrate to remove the remaining liquefied reducing agent and any reaction residual.

    摘要翻译： 提供了形成半导体器件的膜的方法。 该方法包括将液化金属离子源吸附在基板上的步骤; 漂洗衬底以除去未吸附到衬底的任何液化的金属离子源; 通过用液化还原剂还原吸附在基板上的液化金属离子源，在基板上沉积金属层; 并冲洗底物以除去剩余的液化还原剂和任何反应残余物。

    SEMICONDUCTOR DEVICES HAVING METAL INTERCONNECTIONS, SEMICONDUCTOR CLUSTER TOOLS USED IN FABRICATION THEREOF AND METHODS OF FABRICATING THE SAME
    38.
    发明申请
    SEMICONDUCTOR DEVICES HAVING METAL INTERCONNECTIONS, SEMICONDUCTOR CLUSTER TOOLS USED IN FABRICATION THEREOF AND METHODS OF FABRICATING THE SAME 审中-公开
    具有金属互连的半导体器件，其制造中使用的半导体器件工具及其制造方法

    公开(公告)号：US20080174021A1

    公开(公告)日：2008-07-24

    申请号：US12014458

    申请日：2008-01-15

    申请人： Kyung-In Choi ,  Hyun-Bae Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Jong-Won Hong

    发明人： Kyung-In Choi ,  Hyun-Bae Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Jong-Won Hong

    IPC分类号： H01L23/52 ,  H01L21/4763 ,  C23C16/00

    CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76877 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a semiconductor device is provided. The method includes providing a semiconductor substrate having a conductive pattern and forming an insulating layer on the conductive pattern and the semiconductor substrate. The insulating layer is patterned to form an opening which exposes a portion of the conductive pattern. A preliminary diffusion barrier layer is formed on an inner wall of the opening and a top surface of the insulating layer. Oxygen atoms are supplied onto the preliminary diffusion barrier layer to form a first diffusion barrier layer. A metal layer is formed on the first diffusion barrier layer. The metal layer is formed to fill the opening surrounded by the first diffusion barrier layer. A semiconductor device fabricated by the method and a semiconductor cluster tool used in fabrication of the semiconductor device are also provided.

    摘要翻译： 提供一种制造半导体器件的方法。 该方法包括提供具有导电图案的半导体衬底和在导电图案和半导体衬底上形成绝缘层。 图案化绝缘层以形成露出导电图案的一部分的开口。 在开口的内壁和绝缘层的上表面上形成预扩散阻挡层。 将氧原子提供到预扩散阻挡层上以形成第一扩散阻挡层。 金属层形成在第一扩散阻挡层上。 金属层形成为填充由第一扩散阻挡层包围的开口。 还提供了通过该方法制造的半导体器件和用于制造半导体器件的半导体簇工具。

    Conductive Wiring for Semiconductor Devices
    39.
    发明申请
    Conductive Wiring for Semiconductor Devices 审中-公开
    半导体器件的导电布线

    公开(公告)号：US20080122076A1

    公开(公告)日：2008-05-29

    申请号：US11943166

    申请日：2007-11-20

    申请人： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Hyun Park ,  Kyung-In Choi ,  Hyun-Bae Lee

    发明人： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Hyun Park ,  Kyung-In Choi ,  Hyun-Bae Lee

    IPC分类号： H01L23/48

    CPC分类号： H01L27/115 ,  H01J2237/0812 ,  H01L27/11521 ,  H01L27/11524

    摘要： A conductive wiring for a semiconductor device is provided including a semiconductor substrate and a plurality of lower conductive structures on the semiconductor substrate. An insulating layer is provided that electrically insulates the plurality of lower conductive structures from one another. A first insulation interlayer pattern is provided on the insulation layer. The first insulation interlayer pattern includes a contact plug that contacts the substrate through the insulation layer. An etch-stop layer is provided on the contact plug and the first insulation interlayer pattern. A second insulation interlayer pattern is provided on the etch-stop layer. The second insulation interlayer pattern includes a conductive line that is electrically connected to the contact plug. Related methods and flash memory devices are also provided.

    摘要翻译： 在半导体衬底上设置有半导体衬底和多个下导电结构的半导体器件用导电布线。 提供了使多个下导电结构彼此电绝缘的绝缘层。 在绝缘层上设置第一绝缘夹层图案。 第一绝缘层间图案包括通过绝缘层接触衬底的接触插塞。 在接触插塞和第一绝缘层间图案上设置有蚀刻停止层。 在蚀刻停止层上设置第二绝缘层间图案。 第二绝缘层间图案包括电连接到接触插塞的导线。 还提供了相关方法和闪存设备。