-
公开(公告)号：US20090294970A1
公开(公告)日：2009-12-03
申请号：US12130579
申请日：2008-05-30
IPC分类号： H01L23/538
CPC分类号： H01L23/66 , H01L23/522 , H01L23/5222 , H01L23/60 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05095 , H01L2224/05624 , H01L2224/05647 , H01L2224/16 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： An integrated circuit includes a high speed circuit, an interconnect pad, a passivation layer under the interconnect pad, a first patterned metal layer, and a first via. The high speed circuit is for a high speed signal at a terminal of the high speed circuit. The interconnect pad is on a top surface of the integrated circuit structure. The first patterned metal layer is under the passivation layer having a first portion and a second portion. The first portion of the first patterned metal layer is connected to the terminal of the high speed circuit. The second portion of the first patterned metal layer is under the interconnect pad and is electrically floating when the high frequency signal is present on the interconnect pad portion. The result is reduced capacitive loading on the high speed signal which improves performance.
摘要翻译： 集成电路包括高速电路，互连焊盘，互连焊盘下方的钝化层，第一图案化金属层和第一通孔。 高速电路用于在高速电路的端子处的高速信号。 互连焊盘位于集成电路结构的顶表面上。 第一图案化金属层在钝化层下方具有第一部分和第二部分。 第一图案化金属层的第一部分连接到高速电路的端子。 第一图案化金属层的第二部分在互连焊盘下方并且当高频信号存在于互连焊盘部分上时电浮置。 结果是降低了高速信号的电容负载，从而提高了性能。
-
32.发明授权公开(公告)号：US09099475B2
公开(公告)日：2015-08-04
申请号：US13611076
申请日：2012-09-12
IPC分类号： H05K1/00 , H05K7/00 , G02B6/12 , H01L23/02 , H01L23/48 , G11C5/06 , H01L23/538 , H01L25/04 , H01L25/065 , H01L23/00
CPC分类号： H01L23/48 , H01L23/538 , H01L24/16 , H01L24/24 , H01L24/32 , H01L24/73 , H01L24/82 , H01L25/04 , H01L25/0657 , H01L2224/131 , H01L2224/16146 , H01L2224/24146 , H01L2224/245 , H01L2224/2518 , H01L2224/32135 , H01L2224/73217 , H01L2224/73259 , H01L2224/8203 , H01L2224/82101 , H01L2224/83 , H01L2224/9202 , H01L2224/92144 , H01L2224/94 , H01L2224/97 , H01L2225/06541 , H01L2924/00014 , H01L2924/01079 , H01L2924/01029 , H01L2924/01013 , H01L2224/81 , H01L2924/014
摘要： An electronic assembly includes a processor die assembly, a first die assembly, and a second die assembly. The first die assembly is positioned on a first side of the processor die assembly. The second die assembly is positioned on a second side of the processor die assembly opposite the first side of the processor die assembly. Through-die vias couple the first and second die assemblies to the processor die assembly.
摘要翻译： 电子组件包括处理器模具组件，第一模具组件和第二模具组件。 第一模具组件定位在处理器模具组件的第一侧上。 第二模具组件位于处理器模具组件的与处理器模具组件的第一侧相对的第二侧。 通孔将第一和第二模具组件耦合到处理器模具组件。
-
公开(公告)号：US08796822B2
公开(公告)日：2014-08-05
申请号：US13268681
申请日：2011-10-07
IPC分类号： H01L29/40
CPC分类号： H01L25/0657 , H01L21/76898 , H01L22/32 , H01L25/50 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2225/06596
摘要： A stacked semiconductor device includes a first and a second semiconductor device. A first major surface of each of the first and second devices which includes the active circuitry directly face each other. The first major surface of each of the devices includes a beveled edge on at least one edge, and a probe pad which extends onto the beveled edge. A first opening is located between the beveled edges of the first and second devices on a vertical side of the stacked semiconductor device.
摘要翻译： 叠层半导体器件包括第一和第二半导体器件。 第一和第二装置中的每一个的第一主表面包括有源电路直接面对彼此。 每个装置的第一主表面包括在至少一个边缘上的斜边缘和延伸到斜边上的探针垫。 第一开口位于堆叠半导体器件的垂直侧上的第一和第二器件的斜边之间。
-
公开(公告)号：US20130023091A1
公开(公告)日：2013-01-24
申请号：US13189054
申请日：2011-07-22
申请人： George R. Leal , Kevin J. Hess , Trent S. Uehling
发明人： George R. Leal , Kevin J. Hess , Trent S. Uehling
IPC分类号： H01L21/82
CPC分类号： H01L23/585 , H01L23/5256 , H01L24/03 , H01L24/05 , H01L2224/03001 , H01L2224/05556 , H01L2224/45124 , H01L2224/94 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/01074 , H01L2924/12042 , H01L2924/00 , H01L2224/48 , H01L2224/03
摘要： A method for forming a semiconductor structure includes forming a plurality of fuses over a semiconductor substrate; forming a plurality of interconnect layers over the semiconductor substrate and a plurality of interconnect pads at a top surface of the plurality of interconnect layers; and forming a seal ring, wherein the seal ring surrounds active circuitry formed in and on the semiconductor substrate, the plurality of interconnect pads, and the plurality of fuses, wherein each fuse of the plurality of fuses is electrically connected to a corresponding interconnect pad of the plurality of interconnect pads and the seal ring, and wherein when each fuse of the plurality of fuses is in a conductive state, the fuse electrically connects the corresponding interconnect pad to the seal ring.
摘要翻译： 一种形成半导体结构的方法包括在半导体衬底上形成多个熔丝; 在所述半导体衬底上形成多个互连层，以及在所述多个互连层的顶表面处形成多个互连焊盘; 以及形成密封环，其中所述密封环包围形成在所述半导体衬底上，所述多个互连焊盘和所述多个熔丝中的有源电路，其中所述多个熔丝中的每个熔丝被电连接到相应的互连焊盘 所述多个互连焊盘和所述密封环，并且其中当所述多个熔丝中的每个熔丝处于导通状态时，所述熔丝将相应的互连焊盘电连接到所述密封环。
-
公开(公告)号：US08349666B1
公开(公告)日：2013-01-08
申请号：US13189054
申请日：2011-07-22
申请人： George R. Leal , Kevin J. Hess , Trent S. Uehling
发明人： George R. Leal , Kevin J. Hess , Trent S. Uehling
IPC分类号： H01L21/82 , H01L21/332 , H01L21/44 , H01L21/4763
CPC分类号： H01L23/585 , H01L23/5256 , H01L24/03 , H01L24/05 , H01L2224/03001 , H01L2224/05556 , H01L2224/45124 , H01L2224/94 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/01074 , H01L2924/12042 , H01L2924/00 , H01L2224/48 , H01L2224/03
摘要： A method for forming a semiconductor structure includes forming a plurality of fuses over a semiconductor substrate; forming a plurality of interconnect layers over the semiconductor substrate and a plurality of interconnect pads at a top surface of the plurality of interconnect layers; and forming a seal ring, wherein the seal ring surrounds active circuitry formed in and on the semiconductor substrate, the plurality of interconnect pads, and the plurality of fuses, wherein each fuse of the plurality of fuses is electrically connected to a corresponding interconnect pad of the plurality of interconnect pads and the seal ring, and wherein when each fuse of the plurality of fuses is in a conductive state, the fuse electrically connects the corresponding interconnect pad to the seal ring.
摘要翻译： 一种形成半导体结构的方法包括在半导体衬底上形成多个熔丝; 在所述半导体衬底上形成多个互连层，以及在所述多个互连层的顶表面处形成多个互连焊盘; 以及形成密封环，其中所述密封环包围形成在所述半导体衬底上，所述多个互连焊盘和所述多个熔丝中的有源电路，其中所述多个熔丝中的每个熔丝被电连接到相应的互连焊盘 所述多个互连焊盘和所述密封环，并且其中当所述多个熔丝中的每个熔丝处于导通状态时，所述熔丝将相应的互连焊盘电连接到所述密封环。
-
36.发明授权
公开(公告)号：US6093496A
公开(公告)日：2000-07-25
申请号：US76209
申请日：1998-05-12
申请人： Richard Joseph Gilbert Dominguez , Christopher S. Henkee , Kevin J. Hess , Wheeler C. Crawford , Richard J. Clark , Randall K. Evans , Gerald W. Cummings
发明人： Richard Joseph Gilbert Dominguez , Christopher S. Henkee , Kevin J. Hess , Wheeler C. Crawford , Richard J. Clark , Randall K. Evans , Gerald W. Cummings
CPC分类号： D01F6/46 , C08F8/30 , Y10T428/31855 , Y10T442/601 , Y10T442/602 , Y10T442/607
摘要： This invention concerns a composition comprising a blend of polyolefin with the reaction of a functionalized polyolefin and polyetheramine in which the polyetheramine is grafted into the functionalized polyolefin in a customary mixing apparatus. A process for producing the reaction product of functionalized polypropylene and polyetheramine by melting with polypropylene in a customary mixing apparatus is also disclosed. Blends of the present invention are advantageously useful to prepare paintable automotive body parts. This invention further includes dyeable polyolefin compositions containing the reaction product of functionalized polyolefin and polyetheramine. Dyeable polyolefin fibers, including polypropylene fibers, are disclosed, which may be made by melt spinning, and which may be employed to make woven and non-woven fabric. The polyolefin employed in the practice of this invention may be a flexible polyolefin.
摘要翻译： 本发明涉及包含聚烯烃与官能化聚烯烃与聚醚胺反应的共混物的组合物，其中聚醚胺在常规混合装置中接枝到官能化聚烯烃中。 还公开了通过在常规混合装置中用聚丙烯熔化制备官能化聚丙烯和聚醚胺的反应产物的方法。 本发明的共混物有利于制备可涂漆的汽车车身部件。 本发明还包括含有官能化聚烯烃和聚醚胺反应产物的可染色聚烯烃组合物。 公开了包括聚丙烯纤维在内的可染性聚烯烃纤维，其可以通过熔融纺丝制备，并且可以用于制造机织和非织造织物。 用于本发明实践的聚烯烃可以是柔性聚烯烃。
-
公开(公告)号：US5350807A
公开(公告)日：1994-09-27
申请号：US83149
申请日：1993-06-25
申请人： Ted M. Pettijohn , Kevin J. Hess
发明人： Ted M. Pettijohn , Kevin J. Hess
CPC分类号： C08L23/06 , C08L23/0815
摘要： A composition is provided, comprising (1) a narrow molecular weight distribution component having an Mw/Mn in the range of about 1.0 to about 2.0 and a weight average molecular weight in the range of about 500 to about 7,500 comprising an ethylene homopolymer; and (2) a broad molecular weight distribution component having an Mw/Mn greater than or equal to about 3.0 and a weight average molecular weight in the range of about 100,000 to about 750,000 comprising and ethylene copolymer; wherein said narrow molecular weight distribution component is present in the polymer composition in an amount of at least about 10 weight percent as based on the total weight of the polymer composition. In another embodiment, the narrow molecular weight distribution component further comprises an ethylene/hexene copolymer.
摘要翻译： 提供了一种组合物，其包括（1）包含乙烯均聚物的Mw / Mn在约1.0至约2.0范围内且重均分子量在约500至约7,500范围内的窄分子量分布组分; 和（2）Mw / Mn大于或等于约3.0且重均分子量在约100,000至约75,000的范围内的宽分子量分布组分和乙烯共聚物; 其中所述窄分子量分布组分以基于聚合物组合物的总重量为至少约10重量％的量存在于聚合物组合物中。 在另一个实施方案中，窄分子量分布组分还包含乙烯/己烯共聚物。
-
公开(公告)号：US20130088255A1
公开(公告)日：2013-04-11
申请号：US13268681
申请日：2011-10-07
IPC分类号： G01R31/26 , H01L23/48 , H01L23/544
CPC分类号： H01L25/0657 , H01L21/76898 , H01L22/32 , H01L25/50 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2225/06596
摘要： A stacked semiconductor device includes a first and a second semiconductor device. A first major surface of each of the first and second devices which includes the active circuitry directly face each other. The first major surface of each of the devices includes a beveled edge on at least one edge, and a probe pad which extends onto the beveled edge. A first opening is located between the beveled edges of the first and second devices on a vertical side of the stacked semiconductor device.
摘要翻译： 叠层半导体器件包括第一和第二半导体器件。 第一和第二装置中的每一个的第一主表面包括有源电路直接面对彼此。 每个装置的第一主表面包括在至少一个边缘上的斜边缘和延伸到斜边上的探针垫。 第一开口位于堆叠半导体器件的垂直侧上的第一和第二器件的斜边之间。
-
39.发明授权Die level metal density gradient for improved flip chip package reliability 有权芯片级金属密度梯度，提高了倒装芯片的封装可靠性公开(公告)号：US07276435B1
公开(公告)日：2007-10-02
申请号：US11445657
申请日：2006-06-02
申请人： Scott K. Pozder , Kevin J. Hess , Ruiqi Tian , Edward O. Travis , Trent S. Uehling , Brett P. Wilkerson , Katie C. Yu
发明人： Scott K. Pozder , Kevin J. Hess , Ruiqi Tian , Edward O. Travis , Trent S. Uehling , Brett P. Wilkerson , Katie C. Yu
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L24/13 , H01L24/14 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/051 , H01L2224/05572 , H01L2224/056 , H01L2224/13006 , H01L2224/13022 , H01L2224/13076 , H01L2224/13111 , H01L2224/13147 , H01L2224/13171 , H01L2224/13181 , H01L2224/13184 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19043 , H01L2924/00014
摘要： An integrated circuit has metal bumps on the top surface that create a potentially destructive stress on the underlying layers when the metal bumps are formed. Ensuring a minimum metal concentration in the underlying metal interconnect layers has been implemented to reduce the destructive effect. The minimum metal concentration is highest in the corners, next along the border not in the corner, and next is the interior. The regions in an interconnect layer generally under the metal bump require more concentration than adjacent regions not under a bump. Lesser concentration is required for the metal interconnect layers that are further from the surface of the integrated circuit. The desired metal concentration is achieved by first trying a relatively simple solution. If that is not effective, different approaches are attempted until the minimum concentration is reached or until the last approach has been attempted.
摘要翻译： 集成电路在顶表面上具有金属凸块，当形成金属凸块时，在底层上产生潜在的破坏性应力。 确保底层金属互连层中的最小金属浓度得以实现，以减少破坏作用。 最低金属浓度在角落最高，接下来沿着边界不在拐角处，接下来是内部。 通常在金属凸块下方的互连层中的区域需要比不在凸块下方的相邻区域更多的浓度。 对于远离集成电路表面的金属互连层，需要较小的浓度。 所需的金属浓度通过首先尝试相对简单的解决方案实现。 如果没有效果，则尝试不同的方法，直到达到最小浓度，或直到最后一次尝试。
-
40.发明授权公开(公告)号：US09093429B2
公开(公告)日：2015-07-28
申请号：US13535028
申请日：2012-06-27
IPC分类号： H01L23/34 , H01L23/52 , H01L23/48 , H01L23/13 , H01L23/36 , H01L23/367 , H01L23/31 , H01L23/00
CPC分类号： H01L23/481 , H01L23/13 , H01L23/3157 , H01L23/36 , H01L23/3677 , H01L24/48 , H01L2224/2929 , H01L2224/293 , H01L2224/32245 , H01L2224/4824 , H01L2224/73265 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device comprising a substrate, a power bus, a heat source circuit, a heat sensitive circuit, and a plurality of electrically and thermally conductive through-silicon-vias (TSVs) in the substrate. The TSVs are electrically coupled to the power bus and positioned between the heat source circuit and the heat sensitive circuit to absorb heat from the heat source circuit.
摘要翻译： 一种半导体器件，包括衬底，电源总线，热源电路，热敏电路以及衬底中的多个电导热导电通硅通孔（TSV）。 TSV电耦合到电力总线并且位于热源电路和热敏电路之间以吸收来自热源电路的热量。
-
-
-
-
-
-
-
-
-
搜索结果
55 条记录 (耗时 0.027 秒)
