公开(公告)号：US09941260B2

公开(公告)日：2018-04-10

申请号：US15203418

申请日：2016-07-06

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Chi-Chin Lien ,  Nai-Wei Liu ,  I-Hsuan Peng ,  Ching-Wen Hsiao ,  Wei-Che Huang

IPC: H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor package that includes a first semiconductor die having a first surface and a second surface opposite thereto. A first package substrate is disposed on the first surface of the first semiconductor die. A first molding compound surrounds the first semiconductor die and the first package substrate. A first redistribution layer (RDL) structure is disposed on the first molding compound, in which the first package substrate is interposed and electrically coupled between the first semiconductor die and the first RDL structure.

公开(公告)号：US09786560B2

公开(公告)日：2017-10-10

申请号：US15365435

申请日：2016-11-30

Applicant: MediaTek Inc.

Inventor： Cheng-Chou Hung ,  Ming-Tzong Yang ,  Tung-Hsing Lee ,  Wei-Che Huang ,  Yu-Hua Huang ,  Tzu-Hung Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L29/06 ,  H01L21/761 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/76898 ,  H01L21/761 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor package structure is provided. The method for forming a semiconductor package structure includes providing a substrate, wherein the substrate has a front side and a back side, forming a first guard ring doped region and a second guard ring doped region in the substrate, wherein the first guard ring doped region and the second guard ring doped region have different conductive types, forming a trench through the substrate from a back side of the substrate, conformally forming an insulating layer lining the back side of the substrate, a bottom surface and sidewalls of the trench, removing a portion of the insulating layer on the back side of the substrate to form a through via, and forming a conductive material in the through via, wherein a through silicon via (TSV) interconnect structure is formed by the insulating layer and the conductive material.

公开(公告)号：US09633936B2

公开(公告)日：2017-04-25

申请号：US14980445

申请日：2015-12-28

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Tzu-Hung Lin ,  Ta-Jen Yu

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate. First and second conductive traces are disposed on the substrate. A conductive pillar bump is disposed on the second conductive trace, and a first conductive structure is disposed between the second conductive trace and the conductive pillar bump or between the second conductive trace and the substrate. A semiconductor die is disposed over the first conductive trace, wherein the conductive pillar bump connects to the semiconductor die.

公开(公告)号：US20170062388A1

公开(公告)日：2017-03-02

申请号：US15347803

申请日：2016-11-10

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Yu-Hua Huang ,  Wei-Che Huang ,  Ming-Tzong Yang

IPC: H01L25/065 ,  H01L23/00

Abstract: A package structure comprising: a substrate, having at least one conductive units provided at a first surface of the substrate; at least one first die, provided on a second surface of the substrate; a connecting layer, provided on the first die; a second die, provided on the connecting layer, wherein the connecting layer comprises at least one bump for connecting the first die; and at least one bonding wire. The connecting layer has a first touch side and a second touch side, the first touch side contacts a first surface of the first die and the second touch side contacts a second surface of the second die, an area of the first touch side is smaller than which for the first surface of the first die, and a size of the first die equals to which of the second die.

Abstract translation: 一种封装结构，包括：衬底，其具有设置在所述衬底的第一表面处的至少一个导电单元; 至少一个第一管芯，设置在所述衬底的第二表面上; 连接层，设置在第一管芯上; 设置在所述连接层上的第二模具，其中所述连接层包括用于连接所述第一模具的至少一个凸块; 和至少一个接合线。 连接层具有第一触摸侧和第二触摸侧，第一触摸面接触第一模具的第一表面，第二触摸面接触第二模具的第二表面，第一触摸侧的区域小于 对于第一管芯的第一表面和第一管芯的尺寸等于第二管芯的尺寸。

公开(公告)号：US09543232B2

公开(公告)日：2017-01-10

申请号：US14601440

申请日：2015-01-21

Applicant: MediaTek Inc.

Inventor： Cheng-Chou Hung ,  Ming-Tzong Yang ,  Tung-Hsing Lee ,  Wei-Che Huang ,  Yu-Hua Huang ,  Tzu-Hung Lin

IPC: H01L23/48 ,  H01L29/06 ,  H01L21/761 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/761 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package structure and method for forming the same are provided. The semiconductor package structure includes a substrate and the substrate has a front side and a back side. The semiconductor package structure includes a through silicon via (TSV) interconnect structure formed in the substrate; and a first guard ring doped region and a second guard ring doped region formed in the substrate, and the first guard ring doped region and the second guard ring doped region are adjacent to the TSV interconnect structure.

Abstract translation: 提供一种半导体封装结构及其形成方法。 半导体封装结构包括衬底，并且衬底具有正面和背面。 半导体封装结构包括在衬底中形成的穿硅通孔（TSV）互连结构; 以及形成在所述衬底中的第一保护环掺杂区域和第二保护环掺杂区域，并且所述第一保护环掺杂区域和所述第二保护环掺杂区域与所述TSV互连结构相邻。

公开(公告)号：US09437534B2

公开(公告)日：2016-09-06

申请号：US14714331

申请日：2015-05-17

Applicant: MEDIATEK INC.

Inventor： Thomas Matthew Gregorich ,  Tzu-Hung Lin ,  Che-Ya Chou

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05552

Abstract: A flip chip package includes: a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein part of the copper column overhangs the via opening.

Abstract translation: 倒装芯片封装包括：耦合到管芯的载体。 载体包括：用于将载体的表面耦合到载体中的电迹线的至少一个通孔; 以及至少一个电耦合到所述通孔的捕获垫，其中所述捕获垫被电镀在所述通孔上。 模具包括：至少形成在模具表面上的接合焊盘; 以及形成在所述接合焊盘上的至少一个铜柱，用于将所述管芯耦合到所述载体上的捕获垫，其中所述铜柱的一部分突出于所述通孔开口。

公开(公告)号：US09040359B2

公开(公告)日：2015-05-26

申请号：US14482112

申请日：2014-09-10

Applicant: MediaTek Inc.

Inventor： Thomas Matthew Gregorich ,  Andrew C. Chang ,  Tzu-Hung Lin

IPC: H01L21/00 ,  H01L21/4763 ,  H01L27/08 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L21/56 ,  H01L23/367 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method for fabricating a molded interposer package includes performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet, forming a molding material covering the top surface, filling the first recesses, forming a plurality of first via openings in the molding material, wherein the first via openings expose the top surface, forming a plurality of first metal vias in the first via openings and a plurality of first redistribution layer patterns respectively on the first metal vias, performing a second anisotropic etching process to remove a portion of the metal sheet from a bottom surface of the metal sheet until a bottom of the molding material is exposed, and forming a solder mask layer on the molding material, leaving the first redistribution layer patterns exposed.

Abstract translation: 一种用于制造模制插入件封装的方法包括进行第一各向异性蚀刻工艺以从金属板的顶表面去除金属片的一部分，从而在金属片中形成多个第一凹槽，形成覆盖金属片的成型材料 顶表面，填充第一凹槽，在模制材料中形成多个第一通孔，其中第一通孔开口暴露顶表面，在第一通孔中形成多个第一金属通孔，以及多个第一再分配层图案 分别在第一金属通孔上，进行第二各向异性蚀刻工艺以从金属板的底表面去除金属片的一部分，直到模制材料的底部暴露，并且在模制材料上形成焊接掩模层， 留下第一个重分布层图案。

公开(公告)号：US20130140694A1

公开(公告)日：2013-06-06

申请号：US13753537

申请日：2013-01-30

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Thomas Matthew Gregorich

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/0519 ,  H01L2224/05559 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate.

Abstract translation: 倒装芯片封装包括具有管芯附接表面的衬底; 以及安装在所述管芯附接表面上的管芯，其具有与所述衬底相对的所述管芯的有源表面，其中所述管芯经由所述有源表面上的多个铜柱凸起与所述衬底互连，其中所述多个铜柱中的至少一个 凸块具有基本上等于或小于衬底的芯片附接表面上的迹线的线宽的凸起宽度。

公开(公告)号：US12002742B2

公开(公告)日：2024-06-04

申请号：US17838412

申请日：2022-06-13

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Yuan-Chin Liu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49816 ,  H01L23/3192 ,  H01L24/13 ,  H01L24/45 ,  H01L24/73 ,  H01L25/0655

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first semiconductor die, and a second semiconductor die. The substrate includes a first substrate partition and a second substrate partition. The first substrate partition has a first wiring structure. The second substrate partition is adjacent to the first substrate partition and has a second wiring structure. The first substrate partition and the second substrate partition are surrounded by a first molding material. The first semiconductor die is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die is disposed over the substrate and electrically coupled to the second wiring structure.

公开(公告)号：US11862578B2

公开(公告)日：2024-01-02

申请号：US17575789

申请日：2022-01-14

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng Chang ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Yi-Jou Lin

IPC: H01L23/00 ,  H01L23/053 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L23/562 ,  H01L23/053 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/367 ,  H01L23/49822 ,  H01L25/165

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die disposed over the substrate, and a frame disposed over the substrate. The frame is adjacent to the semiconductor die, and an upper surface of the frame is lower than the upper surface of the semiconductor die. IN addition, a passive component is disposed on the substrate and located between the frame and the semiconductor die.