公开(公告)号：US20110233782A1

公开(公告)日：2011-09-29

申请号：US13052769

申请日：2011-03-21

申请人： Shu-Ming CHANG ,  Bai-Yao Lou ,  Ying-Nan Wen ,  Chien-Hung Liu

发明人： Shu-Ming CHANG ,  Bai-Yao Lou ,  Ying-Nan Wen ,  Chien-Hung Liu

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L21/50 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/92 ,  H01L24/93 ,  H01L24/94 ,  H01L33/62 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/03825 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/119 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/32052 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/92142 ,  H01L2224/92143 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/0231 ,  H01L2224/11 ,  H01L2224/1182 ,  H01L2224/03 ,  H01L2224/0382 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

摘要： An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.

摘要翻译： 公开了一种电子器件封装。 该封装包括至少一个具有第一表面和与其相对的第二表面的半导体芯片，其中至少一个再分配层设置在半导体芯片的第一表面上并与至少一个导电焊盘结构电连接。 至少一个邻接部分设置在再分布层上并与其电接触。 钝化层覆盖半导体芯片的第一表面并围绕邻接部分。 将衬底附着到半导体芯片的第二表面上。 还公开了一种电子器件封装的制造方法。

公开(公告)号：US07981727B2

公开(公告)日：2011-07-19

申请号：US11987232

申请日：2007-11-28

申请人： Chien-Hung Liu ,  Sih-Dian Lee

发明人： Chien-Hung Liu ,  Sih-Dian Lee

IPC分类号： H01L21/00

CPC分类号： H01L31/0203 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/13 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14687 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/00

摘要： Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A first trench is formed by etching the semiconductor exposing an inter-layered dielectric layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the first trench is removed to create a second trench. The insulating layer and the ILD layer are sequentially removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an S-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.

摘要翻译： 电子装置晶圆级规包装及其制造方法。 提供了形成有多个电子器件的半导体晶片。 半导体晶片与支撑基板结合。 半导体衬底的背面变薄。 通过蚀刻暴露层间电介质层的半导体形成第一沟槽。 绝缘层顺应地沉积在半导体衬底的背面上。 去除第一沟槽底部的绝缘层以产生第二沟槽。 依次去除绝缘层和ILD层，暴露一对接触焊盘的一部分。 导电层顺应地形成在半导体的背面上。 导电层被图案化之后，导电层和接触垫构成S形连接。 接下来，随后形成外部连接和端子接触焊盘。

公开(公告)号：US07925999B2

公开(公告)日：2011-04-12

申请号：US12140325

申请日：2008-06-17

申请人： Ying-Tso Lai ,  Chien-Hung Liu ,  Shou-Kuo Hsu

发明人： Ying-Tso Lai ,  Chien-Hung Liu ,  Shou-Kuo Hsu

IPC分类号： G06F17/50

CPC分类号： H05K3/0005 ,  G06F17/5077 ,  H05K1/0263 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09718

摘要： A design method of printed circuit boards includes the following steps. First, simulate a printed circuit board including power layers, and vias connected to all the power layers. Then, change connections of the vias that tend to draw too much current to be connected to fewer power layers, than the vias that tend to draw less current. Repeat adjusting connections of the vias until all vias draw a similar amount of current such that no via draws more current than an upper limit the vias are designed for. Finally, according to the results, design/fabricate a PCB with vias respectively insulated, as needed, from the power layers that do not need to be connected to the vias.

摘要翻译： 印刷电路板的设计方法包括以下步骤。 首先，模拟包括电源层的印刷电路板和连接到所有电源层的通孔。 然后，改变通常将过多电流连接到更少功率层的通孔的连接，而不是倾向于减少电流的通孔。 重复调整通孔的连接，直到所有通孔绘制相似的电流量，使得通孔不会超过通孔设计的上限。 最后，根据结果，根据需要，从不需要连接到通孔的电源层设计/制造通孔的PCB分别绝缘。

公开(公告)号：US20100250386A1

公开(公告)日：2010-09-30

申请号：US12458921

申请日：2009-07-28

申请人： Chien-Hung Liu ,  Chi-Chen Cheng

发明人： Chien-Hung Liu ,  Chi-Chen Cheng

IPC分类号： G06F17/30 ,  G06Q30/00

CPC分类号： G06Q30/0601 ,  G06F16/9535

摘要： Method and system for personalizing online content are disclosed. One of the features of the invention is to determine a user's preference based on the information of the network-based digital content downloaded by the user, and accordingly to build a personalized database. In reference with the personalized database, the system will provide the related personalized information. According to the preferred embodiment, a network connection between a user information system and a remote information service platform is established in the beginning. The method then goes to analyze the user's preference from the selected digital content, and build the personalized database. After that, the invention accordingly provides the personalized information relating the preferred video and audio content. The method is preferably adapted to an electronic commercial platform which provides personalized commercial content for further consumption activity as a specific program is used to display the commercial content on a computer screen.

摘要翻译： 公开了个性化在线内容的方法和系统。 本发明的一个特征是基于用户下载的基于网络的数字内容的信息来确定用户的偏好，并因此构建个性化数据库。 参考个性化数据库，系统将提供相关的个性化信息。 根据优选实施例，开始时建立用户信息系统和远程信息服务平台之间的网络连接。 然后，该方法从所选择的数字内容中分析用户的偏好，并构建个性化数据库。 之后，本发明相应地提供了有关优选视频和音频内容的个性化信息。 该方法优选地适用于电子商业平台，其提供用于进一步消费活动的个性化商业内容，因为特定程序用于在计算机屏幕上显示商业内容。

公开(公告)号：US07804122B2

公开(公告)日：2010-09-28

申请号：US12434828

申请日：2009-05-04

申请人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

发明人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

IPC分类号： H01L31/119

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7881 ,  H01L29/792

摘要： A non-volatile memory includes a substrate having two openings, a stacked gate structure disposed on the substrate between the two openings, a liner disposed on a bottom of each of the two openings and parts of a sidewall of each of the two openings, a second conductive layer disposed on the liner at the bottom of each of the two openings, and a third conductive layer on the second conductive layer and the liner. The stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, and a first conductive layer. The liner has a top surface lower than that of the substrate. The second conductive layer has a top surface co-planar with that of the liner. The third conductive layer has a top surface at least co-planar with that of the substrate and lower than that of the first dielectric layer.

摘要翻译： 非易失性存储器包括具有两个开口的衬底，设置在两个开口之间的衬底上的堆叠栅极结构，设置在两个开口中的每一个的底部和两个开口中的每一个的侧壁的一部分的衬垫， 设置在两个开口中的每一个的底部的衬垫上的第二导电层，以及在第二导电层和衬垫上的第三导电层。 层叠栅极结构包括第一介电层，电荷存储层，第二介电层和第一导电层。 衬垫具有比衬底更低的顶表面。 第二导电层具有与衬垫的顶表面共面的顶表面。 第三导电层具有至少与基底的共面的顶表面，并且低于第一介电层的顶表面。

公开(公告)号：US20100055843A1

公开(公告)日：2010-03-04

申请号：US12615159

申请日：2009-11-09

申请人： Chien-Hung Liu

发明人： Chien-Hung Liu

IPC分类号： H01L21/00

CPC分类号： H01L23/3677 ,  H01L23/3114 ,  H01L2924/0002 ,  H01L2924/00

摘要： A heat sink mechanism including multiple heat passages in the base of a casing of a chip package module penetrating through a substrate packed in the module; a metal material being deposited in each heat passage to become a heat sink conductor connecting the substrate and the surface of the casing to effectively solve the problem of excessive heat generated in the course of HF operation of the chip package module thus to prevent chip failure.

摘要翻译： 一种散热机构，包括穿过包装在所述模块中的基板的芯片封装模块的壳体的底部中的多个热通道; 沉积在每个热通道中的金属材料成为连接衬底和壳体表面的散热导体，以有效地解决芯片封装模块的HF操作过程中产生的过多热量的问题，从而防止芯片故障。

公开(公告)号：US20080054322A1

公开(公告)日：2008-03-06

申请号：US11468311

申请日：2006-08-30

申请人： Chien-Hung Liu ,  Shou-Wei Huang ,  Ying-Tso Chen ,  Yu-Tsung Lin

发明人： Chien-Hung Liu ,  Shou-Wei Huang ,  Ying-Tso Chen ,  Yu-Tsung Lin

IPC分类号： H01L29/94

CPC分类号： H01L27/115 ,  H01L27/0207 ,  H01L27/11568

摘要： A memory is provided. The memory includes a substrate, a number of parallel bit lines, a number of parallel word lines and at least a oxide-nitride-oxide (ONO) structure. The bit lines are disposed in the substrate. The word lines are disposed on the substrate. The word lines are crossed with but not perpendicular to the bit lines. The ONO structure is disposed between the word lines and the substrate.

摘要翻译： 提供记忆。 存储器包括衬底，多个并行位线，多个并行字线和至少氧化物 - 氧化物 - 氧化物（ONO）结构。 位线设置在基板中。 字线设置在基板上。 字线与位线交叉但不垂直于位线。 ONO结构设置在字线和衬底之间。

公开(公告)号：US20070117322A1

公开(公告)日：2007-05-24

申请号：US11655259

申请日：2007-01-19

申请人： Chien-Hung Liu

发明人： Chien-Hung Liu

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7923

摘要： A NAND type dual bit nitride read only memory and a method for fabricating thereof are provided. Firstly, a plurality of isolation layers, which are spaced and parallel to each other are formed in the substrate. Next, a plurality of word lines and a plurality of oxide-nitride-oxide (ONO) stack structures are formed on the substrate. The word lines are spaced and parallel to each other, and also the word lines are perpendicular to the isolation layers. Each of the ONO stack structure is located between the corresponding word line and the substrate. And then a plurality of discontinuous bit lines, which are located between the word lines and between the isolation layers are formed on the substrate. The structure of the present invention of the NAND type dual bit nitride read only memory is similar to that of a complementary metal-oxide semiconductor (CMOS), and their fabrication processes are fully compatible.

公开(公告)号：US06787416B2

公开(公告)日：2004-09-07

申请号：US10253039

申请日：2002-09-24

申请人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Hung

发明人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Hung

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： The present invention includes devices and methods to form non-volatile memory cells and peripheral devices, with reduced damage to the electron trapping layer and, optionally, reduced thermal exposure during CMOS processing. Particular aspects of the present invention are described in the claims, specification and drawings.

摘要翻译： 本发明包括用于形成非易失性存储器单元和外围设备的装置和方法，对电子俘获层的损害降低，并且可选地在CMOS处理期间减少热暴露。 在权利要求书，说明书和附图中描述了本发明的特定方面。

公开(公告)号：US06559010B1

公开(公告)日：2003-05-06

申请号：US10003320

申请日：2001-12-06

申请人： Tung-Cheng Kuo ,  Shou-Wei Hwang ,  Chien-Hung Liu ,  Shyi-Shuh Pan

发明人： Tung-Cheng Kuo ,  Shou-Wei Hwang ,  Chien-Hung Liu ,  Shyi-Shuh Pan

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： A method is described for forming a non-volatile memory comprising dividing a substrate into at least a memory array area and a logic device area. An oxide/nitride/oxide (ONO) layer is firstly formed on the substrate, and a photoresist layer is formed on the ONO layer by bit line photo process, and a bit line ion implantation process is performed on the substrate to form the plurality of bit lines structure. Then, a first polysilicon layer is deposited to form a plurality of word lines by word line photo condition. The complementary metal-oxide-semiconductor (CMOS) ONO layer is used to store the charge and the ONO layer is only touched by the photoresist layer once. Furthermore, the separated adjust photo condition of the memory array area and the logic device area can create a safe oxide thickness to solve the problem of leakage path between bit lines to bit lines by using a self-aligned silicide process.

摘要翻译： 描述了一种用于形成非易失性存储器的方法，包括将衬底划分成至少存储器阵列区域和逻辑器件区域。 首先在衬底上形成氧化物/氮化物/氧化物（ONO）层，并且通过位线光刻工艺在ONO层上形成光致抗蚀剂层，并在衬底上进行位线离子注入工艺以形成多个 位线结构。 然后，通过字线照片条件沉积第一多晶硅层以形成多个字线。 互补金属氧化物半导体（CMOS）ONO层用于存储电荷，并且ONO层仅被光致抗蚀剂层触及一次。 此外，存储器阵列区域和逻辑器件区域的分离的调整照相条件可以产生安全的氧化物厚度，以通过使用自对准硅化物处理来解决位线到位线之间的泄漏路径的问题。