摘要:
A method is described for fabricating multiple nanowires of uniform length from a single precursor nucleation particle. The method includes growing a first nanowire segment from a nanoparticle and growing a second nanowire segment between the first nanowire segment and the nanoparticle. The first nanowire segment and the second nanowire segment have a different solubility.
摘要:
A method for making a semiconductor device is described. That method comprises forming on a substrate a buffer layer and a high-k gate dielectric layer, oxidizing the surface of the high-k gate dielectric layer, and then forming a gate electrode on the oxidized high-k gate dielectric layer.
摘要:
A method for making a semiconductor device is described. That method comprises forming a metal oxide layer on a substrate, converting at least part of the metal oxide layer to a metal layer; and oxidizing the metal layer to generate a metal oxide high-k gate dielectric layer.
摘要:
A method is described for selectively treating the properties of a gate dielectric near corners of the gate without altering the gate dielectric in a center region of a gate channel. The method includes providing a structure having a gate opening and depositing a layer of dielectric with a high dielectric constant on a bottom surface and side walls of the gate opening. The corner regions of the high dielectric constant layer formed adjacent to the bottom surface and the side walls of the gate opening are selectively treated without altering the center region of the high dielectric constant layer formed at the bottom surface of the gate opening.
摘要:
Low voltage embedded memory having conductive oxide and electrode stacks is described. For example, a material layer stack for a memory element includes a first conductive electrode. A conductive oxide layer is disposed on the first conductive electrode. The conductive oxide layer has a plurality of oxygen vacancies therein. A second electrode is disposed on the conductive oxide layer.
摘要:
Conductive oxide random access memory (CORAM) cells and methods of fabricating CORAM cells are described. For example, a material layer stack for a memory element includes a first conductive electrode. An insulating layer is disposed on the first conductive oxide and has an opening with sidewalls therein that exposes a portion of the first conductive electrode. A conductive oxide layer is disposed in the opening, on the first conductive electrode and along the sidewalls of the opening. A second electrode is disposed in the opening, on the conductive oxide layer.
摘要:
Low voltage embedded memory having conductive oxide and electrode stacks is described. For example, a material layer stack for a memory element includes a first conductive electrode. A conductive oxide layer is disposed on the first conductive electrode. The conductive oxide layer has a plurality of oxygen vacancies therein. A second electrode is disposed on the conductive oxide layer.
摘要:
Switching current in Spin-Transfer Torque Memory (STTM) can be decreased. A magnetic memory cell is driven with a first pulse on a write line of the memory cell to heat the cell. The cell is then driven with a second pulse on the write line to set the state of the cell.
摘要:
The present disclosure relates to the fabrication of spin transfer torque memory elements for non-volatile microelectronic memory devices. The spin transfer torque memory element may include a magnetic tunneling junction connected with specifically sized and/or shaped fixed magnetic layer that can be positioned in a specific location adjacent a free magnetic layer. The shaped fixed magnetic layer may concentrate current in the free magnetic layer, which may result in a reduction in the critical current needed to switch a bit cell in the spin transfer torque memory element.
摘要:
A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.