公开(公告)号：US11588096B2

公开(公告)日：2023-02-21

申请号：US16092165

申请日：2017-04-11

Applicant: The Regents of the University of California

Inventor： Yuuki Enatsu ,  Chirag Gupta ,  Stacia Keller ,  Umesh K. Mishra ,  Anchal Agarwal

IPC: H01L41/18 ,  H01L33/08 ,  H01L29/36 ,  H01L29/861 ,  H01L29/20 ,  H01L29/205 ,  H01L21/00 ,  H01L41/107 ,  H01L21/02

Abstract: An optoelectronic or electronic device structure, including an active region on or above a polar substrate, wherein the active region comprises a polar p region. The device structure further includes a hole supply region on or above the active region. Holes in the hole supply region are driven by a field into the active region, the field arising at least in part due to a piezoelectric and/or spontaneous polarization field generated by a composition and grading of the active region.

公开(公告)号：US20220399475A1

公开(公告)日：2022-12-15

申请号：US17576716

申请日：2022-01-14

Applicant: The Regents of the University of California

Inventor： Kamruzzaman Khan ,  Elaheh Ahmadi ,  Stacia Keller ,  Christian Wurm ,  Umesh K. Mishra

IPC: H01L33/32 ,  H01L33/00

Abstract: A substrate comprising a III-N base layer comprising a first portion and a second portion, the first portion of the III-N base layer having a first natural lattice constant and a first dislocation density; and a first III-N layer having a second natural lattice constant and a second dislocation density on the III-N base layer, the first III-N layer having a thickness greater than 10 nm. An indium fractional composition of the first III-N layer is greater than 0.1; the second natural lattice constant is at least 1% greater than the first natural lattice constant; a strain-induced lattice constant of the first III-N layer is greater than 1.0055 times the first natural lattice constant; and the second dislocation density is less than 1.5 times the first dislocation density.

公开(公告)号：US10529892B2

公开(公告)日：2020-01-07

申请号：US15698181

申请日：2017-09-07

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Robert M. Farrell, Jr. ,  Troy J. Baker ,  Arpan Chakraborty ,  Benjamin A. Haskell ,  P. Morgan Pattison ,  Rajat Sharma ,  Umesh K. Mishra ,  Steven P. DenBaars ,  James S. Speck ,  Shuji Nakamura

IPC: H01L33/16 ,  H01L33/00 ,  B82Y20/00 ,  C30B23/02 ,  C30B25/18 ,  C30B29/40 ,  H01L21/02 ,  H01S5/32 ,  H01S5/343 ,  H01L33/02 ,  H01S5/042 ,  H01S5/22

Abstract: A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.

公开(公告)号：US20190181329A1

公开(公告)日：2019-06-13

申请号：US16092165

申请日：2017-04-11

Applicant: The Regents of the University of California

Inventor： Yuuki Enatsu ,  Chirag Gupta ,  Stacia Keller ,  Umesh K. Mishra ,  Anchal Agarwal

IPC: H01L41/18 ,  H01L21/02 ,  H01L29/205 ,  H01L29/861 ,  H01L33/08 ,  H01L29/20 ,  H01L29/36

Abstract: An optoelectronic or electronic device structure, including an active region on or above a polar substrate, wherein the active region comprises a polar p region. The device structure further includes a hole supply region on or above the active region. Holes in the hole supply region are driven by a field into the active region, the field arising at least in part due to a piezoelectric and/or spontaneous polarization field generated by a composition and grading of the active region.

公开(公告)号：US10312361B2

公开(公告)日：2019-06-04

申请号：US15344377

申请日：2016-11-04

Applicant: The Regents of the University of California

Inventor： Srabanti Chowdhury ,  Jeonghee Kim ,  Chirag Gupta ,  Stacia Keller ,  Silvia H. Chan ,  Umesh K. Mishra

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L29/423 ,  H01L29/40 ,  H01L29/417 ,  H01L29/06 ,  H01L29/51 ,  H01L29/861

Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

公开(公告)号：US09590088B2

公开(公告)日：2017-03-07

申请号：US14566443

申请日：2014-12-10

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Srabanti Chowdhury ,  Ramya Yeluri ,  Christophe Hurni ,  Umesh K. Mishra ,  Ilan Ben-Yaacov

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/861 ,  H01L29/06 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/417

CPC classification number: H01L29/7787 ,  H01L29/0646 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/66204 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/861

Abstract: A current aperture vertical electron transistor (CAVET) with ammonia (NH3) based molecular beam epitaxy (MBE) grown p-type Gallium Nitride (p-GaN) as a current blocking layer (CBL). Specifically, the CAVET features an active buried Magnesium (Mg) doped GaN layer for current blocking purposes. This structure is very advantageous for high power switching applications and for any device that requires a buried active p-GaN layer for its functionality.

Abstract translation: 具有基于氨（NH3）的分子束外延（MBE）的电流孔径垂直电子晶体管（CAVET）生长的p型氮化镓（p-GaN）作为电流阻挡层（CBL）。 具体来说，CAVET具有用于电流阻塞目的的有源掩埋的镁（Mg）掺杂的GaN层。 这种结构对于大功率开关应用以及需要掩埋有源p-GaN层用于其功能的任何器件是非常有利的。

公开(公告)号：US09076927B2

公开(公告)日：2015-07-07

申请号：US14073698

申请日：2013-11-06

Applicant: The Regents of the University of California

Inventor： Stacia Keller ,  Carl J. Neufeld ,  Umesh K. Mishra ,  Steven P. DenBaars

IPC: H01L33/32 ,  H01L21/02 ,  H01L33/00 ,  H01L31/0735 ,  H01L31/18 ,  H01L33/12

CPC classification number: H01L33/32 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L31/0735 ,  H01L31/1856 ,  H01L33/007 ,  H01L33/12 ,  Y02E10/544

Abstract: A method of fabricating a heterostructure device, including (a) obtaining a first layer or substrate; (b) growing a second layer on the first layer or substrate; and (c) forming the second layer that is at least partially relaxed wherein (1) the first layer and the second layer have the same lattice structure but different lattice constants, (2) the first layer and the second layer form a heterojunction, and (3) the heterojunction forms an active area of a device or serves as a pseudo-substrate for the device.

Abstract translation: 一种制造异质结构器件的方法，包括（a）获得第一层或衬底; （b）在第一层或衬底上生长第二层; （c）形成至少部分松弛的第二层，其中（1）第一层和第二层具有相同的晶格结构但具有不同的晶格常数，（2）第一层和第二层形成异质结，以及 （3）异质结形成器件的有源区，或用作器件的伪衬底。

公开(公告)号：US08878249B2

公开(公告)日：2014-11-04

申请号：US13861808

申请日：2013-04-12

Applicant: The Regents of the University of California

Inventor： Jing Lu ,  Stacia Keller ,  Umesh K. Mishra

IPC: H01L29/66 ,  H01L21/338

CPC classification number: H01L29/778 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02581 ,  H01L21/02584 ,  H01L21/0262 ,  H01L21/8252 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method for growing high mobility, high charge Nitrogen polar (N-polar) or Nitrogen face (In,Al,Ga)N/GaN High Electron Mobility Transistors (HEMTs). The method can provide a successful approach to increase the breakdown voltage and reduce the gate leakage of the N-polar HEMTs, which has great potential to improve the N-polar or N-face HEMTs' high frequency and high power performance.

Abstract translation: 用于生长高迁移率，高电荷氮极（N极）或氮面（In，Al，Ga）N / GaN高电子迁移率晶体管（HEMT）的方法。 该方法可以提供成功的方法来增加击穿电压并降低N-极性HEMT的栅极泄漏，其具有改善N极或N面HEMTs高频和高功率性能的巨大潜力。

公开(公告)号：US20140131730A1

公开(公告)日：2014-05-15

申请号：US14073698

申请日：2013-11-06

Applicant: The Regents of the University of California

Inventor： Stacia Keller ,  Carl J. Neufeld ,  Umesh K. Mishra ,  Steven P. DenBaars

IPC: H01L33/00 ,  H01L33/32

CPC classification number: H01L33/32 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L31/0735 ,  H01L31/1856 ,  H01L33/007 ,  H01L33/12 ,  Y02E10/544

Abstract: A method of fabricating a heterostructure device, including (a) obtaining a first layer or substrate; (b) growing a second layer on the first layer or substrate; and (c) forming the second layer that is at least partially relaxed wherein (1) the first layer and the second layer have the same lattice structure but different lattice constants, (2) the first layer and the second layer form a heterojunction, and (3) the heterojunction forms an active area of a device or serves as a pseudo-substrate for the device.

Abstract translation: 一种制造异质结构器件的方法，包括（a）获得第一层或衬底; （b）在第一层或衬底上生长第二层; （c）形成至少部分松弛的第二层，其中（1）第一层和第二层具有相同的晶格结构但具有不同的晶格常数，（2）第一层和第二层形成异质结，以及 （3）异质结形成器件的有源区，或用作器件的伪衬底。

公开(公告)号：US20130015760A1

公开(公告)日：2013-01-17

申请号：US13622979

申请日：2012-09-19

Applicant: The Regents of the University of California

Inventor： Arpan Chakraborty ,  Likun Shen ,  Umesh K. Mishra

IPC: H05B33/02 ,  H05B33/10

CPC classification number: H01L25/0753 ,  F21K9/00 ,  H01L27/156 ,  H01L33/08 ,  H01L33/14 ,  H01L33/20 ,  H01L33/38 ,  H01L33/385 ,  H01L33/42 ,  H01L33/486 ,  H01L33/62 ,  H01L33/64 ,  H01L2924/0002 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2924/00

Abstract: The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking Each pixel is a square with sides of dimension 1. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.

Abstract translation: 本发明公开了一种排列成阵列的多个交错像素，其具有非常低的串联电阻，并具有改进的电流扩散和改进的散热。每个像素是具有尺寸1侧面的正方形。通过增加周长来使串联电阻最小化 的像素的活动区域。 串联电阻也通过缩小每个像素的台面和n接触之间的空间来最小化。