公开(公告)号：US20150069541A1

公开(公告)日：2015-03-12

申请号：US14023552

申请日：2013-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Chern-Yow Hsu ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.

Abstract translation: 本公开的一些实施例涉及一种实现具有低于某些光刻技术的较低分辨率极限的最小尺寸的磁性随机存取存储器（MRAM）单元的基本均匀图案的方法。 将包含第一和第二聚合物种类的共聚物溶液旋涂在位于基材表面上的异质结构上。 异质结构包括由绝缘层分开的第一和第二铁磁层。 将共聚物溶液自组装成包含第二聚合物种类的微畴图案的相分离材料在包含第一聚合物种类的聚合物基质内。 然后除去第一聚合物物质，留下第二聚合物物质的微畴图案。 通过在利用微畴图案作为硬掩模的同时蚀刻异质结构来形成异质结构内的磁记忆单元的图案。

公开(公告)号：US11832520B2

公开(公告)日：2023-11-28

申请号：US17241620

申请日：2021-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Chiao-Chun Hsu ,  Chung-Yi Yu

IPC: H10N30/053 ,  C23C16/458 ,  C23C16/46 ,  H10N30/067 ,  H10N30/078

CPC classification number: H10N30/053 ,  C23C16/4588 ,  C23C16/46 ,  H10N30/067 ,  H10N30/078

Abstract: In some embodiments, the present disclosure relates to a processing tool that includes a wafer chuck disposed within a hot plate chamber and having an upper surface configured to hold a semiconductor wafer. A heating element is disposed within the wafer chuck and configured to increase a temperature of the wafer chuck. A motor is coupled to the wafer chuck and configured to rotate the wafer chuck around an axis of rotation extending through the upper surface of the wafer chuck. The processing tool further includes control circuitry coupled to the motor and configured to operate the motor to rotate the wafer chuck while the temperature of the wafer chuck is increased to form a piezoelectric layer from a sol-gel solution layer on the semiconductor wafer.

公开(公告)号：US20210067058A1

公开(公告)日：2021-03-04

申请号：US16801350

申请日：2020-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chiao-Chun Hsu ,  Chih-Ming Chen ,  Chung-Yi Yu ,  Lung Yuan Pan

IPC: H02N1/00

Abstract: In some embodiments, the present disclosure relates to a microelectromechanical system (MEMS) comb actuator including a comb structure. The comb structure includes a support layer having a first material and a plurality of protrusions extending away from a first surface of the support layer in a first direction. The plurality of protrusions are also made of the first material. The plurality of protrusions are separated along a second direction parallel to the first surface of the support layer. The MEMS comb actuator may further include a dielectric liner structure that continuously and completely covers the first surface of the support layer and outer surfaces of the plurality of protrusions. The dielectric liner structure includes a connective portion that continuously connects topmost surfaces of at least two of the plurality of protrusions.

公开(公告)号：US10833026B2

公开(公告)日：2020-11-10

申请号：US16386630

申请日：2019-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu

IPC: H01L23/00 ,  H01L21/02 ,  H01L27/108 ,  H01L21/302 ,  H01L49/02 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/78 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00 ,  H01L21/822

Abstract: Some embodiments relate to a method. In this method, a semiconductor wafer having a frontside and a backside is received. A frontside structure is formed on the frontside of the semiconductor wafer. The frontside structure exerts a first wafer-bowing stress that bows the semiconductor wafer by a first bow amount. A characteristic is determined for one or more stress-inducing films to be formed based on the first bow amount. The one or more stress-inducing films are formed with the determined characteristic on the backside of the semiconductor wafer and/or on the frontside of the semiconductor wafer to reduce the first bow amount in the semiconductor wafer.

公开(公告)号：US20180348625A1

公开(公告)日：2018-12-06

申请号：US15687541

申请日：2017-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Cheng-Hsuen Chiang ,  Chih-Ming Chen ,  Huai-Chih Cheng ,  Hao-Ming Chang ,  Hsao Shih ,  Hsin-Yi Yin

IPC: G03F1/26

Abstract: A method of manufacturing a photomask includes at least the following steps. First, a phase shift layer and a hard mask layer are formed on a light transmitting substrate. A predetermined mask pattern is split into a first pattern and a second pattern. A series of processes is performed so that the hard mask layer and the phase shift layer have the first pattern and the second pattern. The series of processes includes at least the following steps. First, a first exposure process for transferring the first pattern is performed. Thereafter, a second exposure process for transferring the second pattern is performed. The first exposure process and the second exposure process are executed by different machines.

公开(公告)号：US20180090631A1

公开(公告)日：2018-03-29

申请号：US15273880

申请日：2016-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Lee-Chuan Tseng ,  Ming Chyi Liu ,  Po-Chun Liu

IPC: H01L31/0352 ,  H01L31/0216 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/02 ,  H01L31/103 ,  H01L31/105 ,  H01L31/18

CPC classification number: H01L31/035281 ,  H01L31/02005 ,  H01L31/02019 ,  H01L31/02161 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/103 ,  H01L31/1037 ,  H01L31/105 ,  H01L31/1808 ,  H01L31/1812

Abstract: Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. A dielectric layer is arranged over an upper surface of the silicon substrate, and extends over outer edges of the well region and includes an opening that leaves an inner portion of the well region exposed. An epitaxial pillar of SiGe or Ge extends upward from the inner portion of the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric sidewall structure surrounds the epitaxial pillar and has a bottom surface that rests on an upper surface of the dielectric layer.

公开(公告)号：US20160204212A1

公开(公告)日：2016-07-14

申请号：US14596487

申请日：2015-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu-Hui Su ,  Chih-Ming Chen ,  Chia-Shiung Tsai ,  Chung-Yi Yu ,  Szu-Yu Wang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L29/42332 ,  H01L21/28273 ,  H01L21/32055 ,  H01L21/321 ,  H01L29/42328 ,  H01L29/42348 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/792

Abstract: A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided.

Abstract translation: 提供了用于闪存单元的量子纳米尖端（QNT）薄膜，例如硅纳米尖端（SiNT）薄膜以增加擦除速度。 QNT薄膜包括布置在第一介电层上的第一电介质层和第二电介质层。 此外，QNT薄膜包括布置在第一介电层上并延伸到第二介电层中的QNT。 QNT的高度与宽度之比大于50％。 还提供了基于QNT的闪存单元和用于制造基于SiNT的快闪存储单元的方法。

公开(公告)号：US20160087106A1

公开(公告)日：2016-03-24

申请号：US14489902

申请日：2014-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Tsu-Hui Su ,  Szu-Yu Wang ,  Chung-Yi Yu

IPC: H01L29/788 ,  H01L29/40 ,  H01L29/66 ,  H01L29/792 ,  H01L29/423

CPC classification number: H01L29/7883 ,  G11C16/0483 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure relates to a structure and method for forming a flash memory cell with an improved erase speed and erase current. Si dots are used for charge trapping and an ONO sandwich structure is formed over the Si dots. Erase operation includes direct tunneling as well as FN tunneling which helps increase erase speed without compensating data retention.

Abstract translation: 本发明涉及用于形成具有改进的擦除速度和擦除电流的闪存单元的结构和方法。 Si点用于电荷俘获，并且在Si点上形成ONO夹层结构。 擦除操作包括直接隧道和FN隧道，这有助于提高擦除速度，而不会补偿数据保留。

公开(公告)号：US20150371994A1

公开(公告)日：2015-12-24

申请号：US14308808

申请日：2014-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu-Hui Su ,  Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

Abstract: Some embodiments of the present disclosure relate to a method for forming flash memory. In this method, a first tunnel oxide is formed over a semiconductor substrate. A self-assembled monolayer (SAM) is then formed on the first tunnel oxide. The SAM includes spherical or spherical-like crystalline silicon dots having respective diameters which are less than approximately 30 nm. A second tunnel oxide is then formed over the SAM.

Abstract translation: 本公开的一些实施例涉及用于形成快闪存储器的方法。 在该方法中，在半导体衬底上形成第一隧道氧化物。 然后在第一隧道氧化物上形成自组装单层（SAM）。 SAM包括具有小于约30nm的相应直径的球形或球形晶体硅点。 然后在SAM上形成第二隧道氧化物。

公开(公告)号：US09184041B2

公开(公告)日：2015-11-10

申请号：US13925940

申请日：2013-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu

IPC: H01L21/02 ,  H01L21/822

CPC classification number: H01L23/562 ,  H01L21/02016 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/302 ,  H01L21/30625 ,  H01L21/3205 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L21/8221 ,  H01L22/20 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/10829 ,  H01L27/10861 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit.

Abstract translation: 由深沟槽电容器引起的晶片弯曲由晶片背面形成的结构改善。 反面的结构包括拉伸膜。 膜可以形成在晶片背面的沟槽内，这增强了它们的作用。 在一些实施例中，晶片用于形成3D-IC器件。 在一些实施例中，3D-IC器件包括高电压或高功率电路。