公开(公告)号：US20020074644A1

公开(公告)日：2002-06-20

申请号：US09741206

申请日：2000-12-19

发明人： Robert L. Sankman

IPC分类号： H01L023/053 ,  H01L023/12

CPC分类号： H05K3/4038 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K3/4602 ,  H05K2201/1028 ,  H05K2203/0235 ,  H01L2224/05599

摘要： A microelectronic substrate having a plurality of alternating substantially planar layers of dielectric material and conductive material, and further having a first surface and a second surface, wherein the dielectric material and the conductive material layers extend substantially perpendicularly between the first and second surfaces.

摘要翻译： 一种微电子衬底，其具有多个交替的基本平坦的电介质材料和导电材料层，并且还具有第一表面和第二表面，其中所述电介质材料和所述导电材料层在所述第一表面和所述第二表面之间基本垂直地延伸。

公开(公告)号：US06271483B1

公开(公告)日：2001-08-07

申请号：US09202432

申请日：1998-12-15

申请人： Michio Horiuchi ,  Toshiaki Suyama ,  Masakuni Tokita

发明人： Michio Horiuchi ,  Toshiaki Suyama ,  Masakuni Tokita

IPC分类号： H06R909

CPC分类号： H01L23/49827 ,  H01L2223/6622 ,  H01L2924/0002 ,  H01L2924/15174 ,  H05K1/112 ,  H05K1/115 ,  H05K3/4038 ,  H05K2201/09836 ,  H05K2201/10287 ,  H05K2201/10977 ,  H05K2203/0235 ,  H01L2924/00

摘要： A wiring board has vias which penetrate the wiring board from one side to the other side. The vias are radially arranged in the direction from one side to the other side so that the interval between the vias on one side can be made smaller than the interval between the vias on the other side. In order to prevent the vias from being electrically short-circuited to each other, even if the interval between the vias provided on one side of the wiring board is extremely reduced, a plurality of vias are radially arranged in the direction from one side of the wiring board to the other side so that an interval between the vias on one side of the wiring board can be made smaller than interval of the vias on the other side. A conductor forming the core portion of the via is coated with a sheath portion made of insulating material.

摘要翻译： 布线板具有从一侧到另一侧穿过布线板的通孔。 通孔沿从一侧到另一侧的方向径向布置，使得一侧的通孔之间的间隔可以小于另一侧的通孔之间的间隔。 为了防止通孔彼此电短路，即使设置在布线板的一侧上的通孔之间的间隔极大地减小，多个通孔沿着从一侧的方向 将布线板连接到另一侧，使得布线板一侧的通路之间的间隔可以小于另一侧的通孔的间隔。 形成通孔的芯部的导体涂覆有由绝缘材料制成的护套部分。

公开(公告)号：US5838567A

公开(公告)日：1998-11-17

申请号：US677989

申请日：1996-07-10

申请人： Robert F. Boggio, Jr.

发明人： Robert F. Boggio, Jr.

IPC分类号： G06F17/50 ,  H05K3/00 ,  H05K3/12 ,  H05K3/46 ,  G06F19/00

CPC分类号： H05K3/1241 ,  H05K3/00 ,  H05K2201/09836 ,  H05K2203/0235 ,  Y10T29/53174

摘要： Circuit boards are fabricated in an incremental fashion. Conventional design data representing a layout of the circuit board is received. The design data is transformed into a three-dimensional matrix of increments (e.g., cubes) representing the circuit board, where each increment or cube within the matrix is identified by an address and is assigned a fabrication material. The circuit board is then built at a fabrication station by depositing the assigned fabrication materials onto a fabrication base in an incremental fashion as indicated by the matrix.

摘要翻译： 电路板以渐进的方式制造。 接收表示电路板布局的常规设计数据。 将设计数据变换成表示电路板的增量（例如，立方体）的三维矩阵，其中矩阵内的每个增量或立方体由地址标识并被分配制造材料。 然后，电路板通过以基体表示的递增方式将所分配的制造材料沉积到制造基座上而在制造工地构建。

公开(公告)号：US5531945A

公开(公告)日：1996-07-02

申请号：US246497

申请日：1994-05-20

申请人： Kazuyuki Ohya ,  Norio Sayama

发明人： Kazuyuki Ohya ,  Norio Sayama

IPC分类号： C04B35/622 ,  H01L23/15 ,  H05K1/03 ,  H05K3/00 ,  C04B41/81 ,  B28B11/02

CPC分类号： C04B35/622 ,  H01L23/15 ,  H05K3/0011 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K2201/0116 ,  H05K2203/0235 ,  H05K2203/1147

摘要： A process is provided for the production of a base board for printed wiring. The process involves the steps of wrapping a block inorganic continuous porous material with a cloth, impregnating the wrapped block inorganic continuous porous material with a thermosetting resin under reduced pressure, curing the thermosetting resin to form a composite material, and slicing the composite material into base boards having a thickness of 0.2 to 2 mm and a thickness allowance of .+-.5 .mu.m or less, or the steps of impregnating a block inorganic continuous porous material with a thermosetting resin in an impregnation vessel under reduced pressure, taking the block inorganic continuous porous material impregnated from the impregnation vessel, substantially removing the thermosetting resin adhering to surfaces of the block inorganic continuous porous material before the thermosetting resin forms a gel, curing the remaining thermosetting resin under heat to form a composite material, and slicing the composite material into base boards having a thickness of 0.2 to 2 mm and a thickness allowance of .+-.5 .mu.m or less.

摘要翻译： 提供了一种用于生产用于印刷布线的基板的工艺。 该方法包括以下步骤：用布包裹块状无机连续多孔材料，用热固性树脂在减压下浸渍包裹的无机连续多孔材料，固化热固性树脂以形成复合材料，并将复合材料切成基底 厚度为0.2〜2mm，厚度允许量为+/-5μm以下的板材，或者在浸渍容器内用减压下浸渍嵌段无机连续多孔材料的工序， 从浸渍容器浸渍的连续多孔材料，在热固性树脂形成凝胶之前基本上除去附着在块状无机连续多孔材料的表面上的热固性树脂，在剩余的热固性树脂加热下固化以形成复合材料，并将复合材料 进入具有0.2至2mm厚度的基板 山楂津贴+/- 5亩以下。

公开(公告)号：US4837407A

公开(公告)日：1989-06-06

申请号：US31555

申请日：1987-03-30

申请人： Shinji Nezu

发明人： Shinji Nezu

IPC分类号： H01B19/00 ,  H01B17/60 ,  H01L23/14 ,  H01L23/373 ,  H05K1/03 ,  H05K1/05 ,  H05K3/00

CPC分类号： H01L23/3737 ,  H01L23/145 ,  H05K1/0313 ,  H05K1/056 ,  H05K3/0011 ,  H01L2924/0002 ,  H05K2201/0141 ,  H05K2203/0235 ,  H05K2203/0271 ,  Y10S428/901

摘要： A plastic electrically insulating substrate, having high thermal conductivity, for wiring circuit boards including a substrate having a front surface for mounting an electrical device back surface.The substrate is made of a laminate of a plurality of oriented sheets of one or more semicrystalline polymers having a uniform oriented direction of the sheets, and wherein the oriented direction of the sheets is arranged in the direction of the substrate thickness.

摘要翻译： 一种具有高导热性的塑料电绝缘基板，用于布线电路板，包括具有用于安装电气装置背面的前表面的基板。 基板由具有均匀的片材取向方向的一种或多种半结晶聚合物的多个定向片材的层压体制成，并且其中片材的取向方向沿着基底厚度的方向布置。

公开(公告)号：US4778950A

公开(公告)日：1988-10-18

申请号：US853313

申请日：1986-04-17

申请人： James C. K. Lee ,  Richard Beck ,  Chune Lee ,  Edward Hu

发明人： James C. K. Lee ,  Richard Beck ,  Chune Lee ,  Edward Hu

IPC分类号： H01B5/16 ,  H01L25/065 ,  H01R11/01 ,  H01R13/24 ,  H01R43/00 ,  H01R43/16 ,  H05K3/40 ,  H01B7/00

CPC分类号： H01R13/2414 ,  H01L25/0657 ,  H01R43/007 ,  H05K3/4007 ,  H05K3/4038 ,  H01L2224/45147 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06579 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/15312 ,  H01R43/16 ,  H05K2201/0133 ,  H05K2201/0281 ,  H05K2203/0235 ,  Y10T29/435

摘要： Electronic assemblies are fabricated by stacking alternate connecting layers and component layers. The component layers may be virtually any rigid structure having contact regions formed on at least one face thereof. The connecting layers are formed from anisotropic elastomeric conductors which in turn are fabricated by stacking a plurality of conductive sheets and insulating sheets, where the conductive sheets have a plurality of parallel electrically conductive elements formed therein. By introducing a curable elastomeric resin into the stacked structure so formed, and then curing the elastomer, a solid elastomeric block having a plurality of parallel electrically conductive elements running its length is obtained. Individual elastomeric conductors suitable as connecting layers interfacing between adjacent component layers are obtained by slicing the block in a direction perpendicular to the conductors.

摘要翻译： 电子组件通过堆叠交替的连接层和组件层来制造。 组件层可以是几乎任何刚性结构，其具有形成在其至少一个面上的接触区域。 连接层由各向异性弹性体导体形成，其又通过堆叠多个导电片和绝缘片来制造，其中导电片在其中形成有多个平行的导电元件。 通过将可固化弹性体树脂引入到如此形成的层叠结构中，然后固化弹性体，获得具有多个平行导电元件延伸其长度的固体弹性体块。 通过在垂直于导体的方向上切割块来获得适合作为相邻部件层之间连接的连接层的各个弹性体导体。

公开(公告)号：US20240188228A1

公开(公告)日：2024-06-06

申请号：US18441702

申请日：2024-02-14

申请人： IBIDEN CO., LTD.

发明人： Yuji KADOWAKI ,  Tomomi KANO

IPC分类号： H05K3/46 ,  H05K3/10 ,  H05K3/14

CPC分类号： H05K3/4629 ,  H05K3/106 ,  H05K3/108 ,  H05K3/143 ,  H05K3/4602 ,  H05K2203/0143 ,  H05K2203/0235 ,  H05K2203/065 ,  H05K2203/068 ,  H05K2203/08

摘要： A method for manufacturing a printed wiring board includes forming a seed layer on a surface of a resin insulating layer, applying a dry film onto the seed layer using a laminating roll device, cutting the dry film applied onto the seed layer to a predetermined size, applying pressure and heat to the dry film, forming a plating resist on the seed layer from the dry film using photographic technology, forming an electrolytic plating film on part of the seed layer exposed from the resist, removing the resist from the seed layer, and removing the part of the seed layer exposed from the electrolytic plating film. The applying of the pressure and heat includes applying the pressure and heat to the dry film applied onto the seed layer such that the pressure and heat are applied to the entire surface of the dry film cut to the predetermined size simultaneously.

公开(公告)号：US08988895B2

公开(公告)日：2015-03-24

申请号：US13215725

申请日：2011-08-23

申请人： Ilyas Mohammed ,  Belgacem Haba

发明人： Ilyas Mohammed ,  Belgacem Haba

IPC分类号： H05K7/04 ,  H01B7/00 ,  H01R43/00 ,  H01L21/50 ,  H05K3/46 ,  H01L23/498 ,  H01L21/48 ,  H01R12/52

CPC分类号： H05K3/4602 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01R12/523 ,  H05K2201/10378 ,  H05K2203/0235 ,  Y10T29/49176

摘要： An interconnection element is disclosed that includes a plurality of drawn metal conductors, a dielectric layer, and opposed surfaces having a plurality of wettable contacts thereon. The conductors may include grains having lengths oriented in a direction between the first and second ends of the conductors. A dielectric layer for insulating the conductors may have first and second opposed surfaces and a thickness less than 1 millimeter between the first and second surface. One or more conductors may be configured to carry a signal to or from a microelectronic element. First and second wettable contacts may be used to bond the interconnection element to at least one of a microelectronic element and a circuit panel. The wettable contacts may match a spatial distribution of element contacts at a face of a microelectronic element or of circuit contacts exposed at a face of component other than the microelectronic element.

摘要翻译： 公开了一种互连元件，其包括多个拉制的金属导体，电介质层和在其上具有多个可湿接触点的相对表面。 导体可以包括具有沿导体的第一和第二端之间的方向定向的长度的晶粒。 用于绝缘导体的电介质层可以具有第一和第二相对表面，并且在第一和第二表面之间可以具有小于1毫米的厚度。 一个或多个导体可以被配置为将信号传送到微电子元件或从微电子元件传送信号。 可以使用第一和第二可湿触点将互连元件接合到微电子元件和电路板中的至少一个。 可湿性触点可以匹配微电子元件的表面处的元件触点的空间分布或暴露在微电子元件以外的部件的表面处的电路触点。

公开(公告)号：US20080053690A1

公开(公告)日：2008-03-06

申请号：US11755726

申请日：2007-05-30

申请人： Guo-Cheng Liao

发明人： Guo-Cheng Liao

IPC分类号： H05K1/16 ,  H05K3/00

CPC分类号： H05K1/162 ,  H01G4/012 ,  H01G4/224 ,  H01G4/30 ,  H05K2203/0235 ,  Y10T29/49124

摘要： A manufacturing method and structure for substrate with vertically embedded capacitors includes the steps of providing a plurality of conductive layers having a first dielectric layer and a leading wire layer formed on the first dielectric layer, providing a plurality of composite layers having a second dielectric layer and a patterned electrode layer formed on the second dielectric layer, laminating the conductive layers and the composite layers to form a block which defines a plurality of substrates with vertically embedded capacitors and a plurality of sawing streets between the substrates, and sawing the block along the sawing streets to singularize the substrates.

摘要翻译： 具有垂直嵌入式电容器的基板的制造方法和结构包括以下步骤：提供具有形成在第一介电层上的第一介电层和引线层的多个导电层，提供多个具有第二介电层的复合层， 形成在第二电介质层上的图案化电极层，层叠导电层和复合层以形成限定多个具有垂直嵌入式电容器的基板的块，以及在基板之间的多个锯切街道，以及沿着锯切锯 街道将基底单数化。

公开(公告)号：US20070145551A1

公开(公告)日：2007-06-28

申请号：US11567804

申请日：2006-12-07

申请人： Yoshiyuki Yamaji ,  Hirokazu Noma ,  Hiroyuki Mori

发明人： Yoshiyuki Yamaji ,  Hirokazu Noma ,  Hiroyuki Mori

IPC分类号： H01L23/02

CPC分类号： H01L21/6835 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2224/11003 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/30105 ,  H05K1/0216 ,  H05K3/4015 ,  H05K3/4602 ,  H05K2201/0367 ,  H05K2201/0792 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2201/09909 ,  H05K2201/09981 ,  H05K2203/0113 ,  H05K2203/0235 ,  H05K2203/0338 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149

摘要： A semiconductor package that has a superior high frequency characteristics and that can obtain a large area for an internal wiring pattern is provided. According to the present invention, a semiconductor package includes: a multilayer printed wiring board 12, and an IC chip, mounted on the obverse face of the multilayer wiring board 12, and multiple bump terminals 16, mounted on the reverse face. Each bump terminal 16 includes an insulating core 42 having a flat face 40 and a conductive coating deposited on all external surfaces except that of the flat face 40. The end faces of the conductive coatings 44 appear like rings around the insulating cores 42, and are soldered to annular connection pads 52 formed on the reverse face of the multilayer printed wiring board 12. Vias 36 are arranged immediately above the bump terminals 16, and clearance holes 34, the diameter of which is smaller than the diameter of the bump terminals 16, are formed in internal wiring patterns 28 and 30 to permit the passage of the vias 36.

摘要翻译： 提供了具有优异的高频特性并且可以获得用于内部布线图案的大面积的半导体封装。 根据本发明，半导体封装包括：安装在多层布线板12的正面上的多层印刷布线板12和IC芯片以及安装在反面上的多个凸点端子16。 每个凸块端子16包括具有平坦面40的绝缘芯42和沉积在除了平面40之外的所有外表面上的导电涂层。 导电涂层44的端面看起来像围绕绝缘芯42的环，并且被焊接到形成在多层印刷线路板12的背面上的环形连接焊盘52。 通孔36布置在凸块端子16的正上方，并且其直径小于凸点端子16的直径的间隙孔34形成在内部布线图形28和30中以允许通孔36通过。