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    Processor memory system
    392.
    发明授权
    Processor memory system 有权

    公开(公告)号：US09836412B2

    公开(公告)日：2017-12-05

    申请号：US14707166

    申请日：2015-05-08

    Applicant: Rambus Inc.

    Inventor： Ray McConnell

    IPC: G06F12/10 ,  G06F12/109 ,  G06F11/30 ,  G06F9/46 ,  G06F15/173 ,  G06F15/80

    CPC classification number: G06F13/1657 ,  G06F9/46 ,  G06F11/3017 ,  G06F12/109 ,  G06F15/17337 ,  G06F15/8015 ,  G06F2212/657

    Abstract: A plurality of processing elements (PEs) include memory local to at least one of the processing elements in a data packet-switched network interconnecting the processing elements and the memory to enable any of the PEs to access the memory. The network consists of nodes arranged linearly or in a grid to connect the PEs and their local memories to a common controller. The processor performs memory accesses on data stored in the memory in response to control signals sent by the controller to the memory. The local memories share the same memory map or space. The packet-switched network supports multiple concurrent transfers between PEs and memory. Memory accesses include block and/or broadcast read and write operations, in which data can be replicated within the nodes and, according to the operation, written into the shared memory or into the local PE memory.

    MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORT
    394.
    发明申请
    MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORT 审中-公开

    公开(公告)号：US20170344275A1

    公开(公告)日：2017-11-30

    申请号：US15529970

    申请日：2015-12-18

    Applicant: Rambus Inc.

    Inventor： Frederick A. WARE ,  Ely TSERN

    IPC: G06F3/06 ,  G06F12/06

    CPC classification number: G06F3/0611 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0607 ,  G11C5/04 ,  G11C7/10

    Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.

    Memory Systems, Modules, and Methods for Improved Capacity
    398.
    发明申请
    Memory Systems, Modules, and Methods for Improved Capacity 审中-公开

    公开(公告)号：US20170337014A1

    公开(公告)日：2017-11-23

    申请号：US15522164

    申请日：2015-11-04

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Scott C. Best

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/1673 ,  G11C5/04 ,  Y02D10/14

    Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.

    Memory components and controllers that calibrate multiphase synchronous timing references
    399.
    发明授权
    Memory components and controllers that calibrate multiphase synchronous timing references 有权

    公开(公告)号：US09824730B2

    公开(公告)日：2017-11-21

    申请号：US15228644

    申请日：2016-08-04

    Applicant: Rambus Inc.

    Inventor： Thomas Giovannini ,  Scott C Best ,  Lei Luo ,  Ian Shaeffer

    IPC: G06F12/00 ,  G11C7/22 ,  G11C29/02 ,  G11C29/50 ,  G11C29/56

    CPC classification number: G11C7/222 ,  G11C7/227 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/56

    Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

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