公开(公告)号：US20170070687A1

公开(公告)日：2017-03-09

申请号：US15244297

申请日：2016-08-23

Applicant: Rambus Inc.

Inventor： Jay Endsley

IPC: H04N5/33 ,  H04N5/225 ,  H04N9/04 ,  G02B5/18

CPC classification number: H04N9/045 ,  G02B5/1814 ,  G02B5/1819 ,  G02B5/1871 ,  G02B13/16 ,  H04N5/2254 ,  H04N5/2256

Abstract: An imaging system includes a refractive optical element and one or more diffractive optical gratings disposed over a two-dimensional array of photosensitive pixels. The different gratings present different patterns and features that are tailored to produce point-spread responses that emphasize different properties of an imaged scene. The different responses are captured by the pixels, and data captured from the responses can be used separately or together to analyze aspects of the scene. The imaging systems can include circuitry to analyze the image data, and to support modes that select between point-spread responses, selections of the pixels, and algorithms for analyzing image data.

Abstract translation: 成像系统包括折射光学元件和设置在光敏像素的二维阵列上的一个或多个衍射光栅。 不同的光栅呈现出不同的图案和特征，其被定制以产生强调成像场景的不同属性的点扩展响应。 不同的响应由像素捕获，并且从响应中捕获的数据可以单独使用或一起使用来分析场景的各个方面。 成像系统可以包括用于分析图像数据的电路，以及支持在点扩展响应，像素选择以及用于分析图像数据的算法之间进行选择的模式。

公开(公告)号：US20170070369A1

公开(公告)日：2017-03-09

申请号：US15209375

申请日：2016-07-13

Applicant: Rambus Inc.

Inventor： Chintan S. Thakkar ,  Kun-Yung Chang ,  Ting Wu

IPC: H04L25/03 ,  H04L7/00

CPC classification number: H04L25/03057 ,  H04L7/0045 ,  H04L7/0058 ,  H04L7/0087 ,  H04L25/03063 ,  H04L2025/03369

Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.

Abstract translation: 多相部分响应接收器通过在至少两个时钟相位中选择的一个采样PrDFE输出值来支持各种输入数据速率。 该接收机包括一个校准电路，该校准电路对电路中的关键数据路径进行定时分析，然后使用该分析来选择用于锁存输出值的特定时钟相位。 这些技术允许来自部分响应接收机的每个相位的多路复用器输出直接驱动用于随后阶段的多路复用器的选择，即通过避免各个多路复用器输出中的不稳定性或不确定性的区域。

公开(公告)号：US20170054576A1

公开(公告)日：2017-02-23

申请号：US15259662

申请日：2016-09-08

Applicant: Rambus Inc.

Inventor： Qi Lin ,  Brian Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Kyung Suk Oh ,  Jared L. Zerbe

IPC: H04L25/03 ,  H04L12/26 ,  H04L7/00

CPC classification number: H04L25/03254 ,  H04L7/0025 ,  H04L7/0054 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0331 ,  H04L25/03057 ,  H04L25/03885 ,  H04L43/028 ,  H04L2025/03617

Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

Abstract translation: 接收器配备有自适应相位偏移控制器和相关联的定时校准电路，其一起移动数据采样器和数字均衡器的定时。 样本和均衡器定时被转移到具有相对于当前符号的残余符号间干扰（ISI）能量较少的位置。 可以使用信号质量的测量（诸如接收机比特错误率或滤波器抽头值的比较）来计算移位的位置，以优化数据恢复的定时。

公开(公告)号：US20170052845A1

公开(公告)日：2017-02-23

申请号：US15250677

申请日：2016-08-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern

IPC: G06F11/10 ,  G11C29/52 ,  G06F11/16 ,  G11C7/10 ,  H03M13/15 ,  G11C29/44 ,  G11C29/00

CPC classification number: G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1666 ,  G06F11/20 ,  G11C7/10 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/70 ,  G11C29/765 ,  G11C2029/4402 ,  H03M13/1575

Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

Abstract translation: 公开了一种存储器模块，其包括衬底，输出读取数据的存储器件和缓冲器。 缓冲器具有用于将读取的数据传送到存储器控制器的主界面和耦合到存储器设备的辅助接口以接收读取的数据。 缓冲器包括用于识别所接收的读取数据中的错误并识别与该错误相关联的存储器件中的存储单元位置的错误逻辑。 修复逻辑将替换存储元素映射为与错误相关联的存储单元位置的替代存储元素。

公开(公告)号：US20170052584A1

公开(公告)日：2017-02-23

申请号：US15248364

申请日：2016-08-26

Applicant: RAMBUS INC.

Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

IPC: G06F1/32 ,  G11C7/10 ,  G06F5/06 ,  G11C7/22

CPC classification number: G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F5/065 ,  G06F2205/067 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2272 ,  H03L7/0816

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

Abstract translation: 实施例通常涉及存储器件。 在一个实施例中，存储器件包括时钟接收器电路，其接收外部时钟信号并提供内部时钟信号。 存储装置还包括具有输入的延迟锁定环路电路（DLL）和接收内部时钟信号的电路。 该电路选择内部时钟信号的哪些脉冲被施加到DLL的输入端，使得从外部时钟信号的至少三个连续脉冲中选出的不超过两个时钟脉冲在预定的时间内被施加到DLL的输入 间隔。 在另一个实施例中，一种方法包括在时钟接收器电路处接收外部时钟信号，从时钟接收器电路接收内部时钟信号，以及选择内部时钟信号的哪些脉冲被施加到DLL的输入，其中不再有 从外部时钟信号的至少三个连续脉冲中选择的两个时钟脉冲在预定间隔期间被施加到DLL的输入端。

公开(公告)号：US20170047108A1

公开(公告)日：2017-02-16

申请号：US15242423

申请日：2016-08-19

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G06F1/32 ,  G06F1/08 ,  G11C11/408

CPC classification number: G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/128 ,  Y02D50/20

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

Abstract translation: 集成电路包括具有控制定时域和数据定时域的物理层接口，以及响应于第一事件而在功率节省模式改变期间实现控制定时域的电路，并且响应于数据定时域 到第二个事件。 控制定时域可以包括耦合到命令和地址路径的接口电路，并且数据定时域可以包括耦合到数据路径的接口电路。

公开(公告)号：US09570146B1

公开(公告)日：2017-02-14

申请号：US14181422

申请日：2014-02-14

Applicant: Rambus Inc.

Inventor： Christopher Haywood

IPC: G06F13/12 ,  G06F13/38 ,  G11C11/406

CPC classification number: G11C7/20 ,  G11C7/22 ,  G11C7/227 ,  G11C11/406 ,  G11C11/40611

Abstract: A method for operating a DRAM is provided. The method includes initializing a dynamic random access memory (“DRAM”) array from a host controller, which is coupled to the DRAM array. The method includes isolating the dynamic random access memory array from a host controller and allowing a host computer to wait for a selected time period greater than the tRFC to define an alternate access time. The method includes initiating an access command to the DRAM array during the alternate access time.

Abstract translation: 提供了一种用于操作DRAM的方法。 该方法包括从耦合到DRAM阵列的主机控制器初始化动态随机存取存储器（“DRAM”）阵列。 该方法包括从主机控制器隔离动态随机存取存储器阵列并允许主计算机等待大于tRFC的选定时间段以定义备用访问时间。 该方法包括在替代访问时间期间启动对DRAM阵列的访问命令。

公开(公告)号：US09570144B2

公开(公告)日：2017-02-14

申请号：US15046820

申请日：2016-02-18

Applicant: Rambus Inc.

Inventor： Richard Perego ,  Thomas Vogelsang ,  John Brooks

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/406 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/408 ,  G11C2211/4061

Abstract: The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.

Abstract translation: 本公开描述了DRAM架构和刷新控制器，其允许与指向DRAM设备的正常行激活命令同时调度DRAM设备的机会性刷新。 每个激活命令提供了在没有调度冲突的情况下刷新存储器设备内的另一独立行（即字线）的“机会”。

公开(公告)号：US09552865B2

公开(公告)日：2017-01-24

申请号：US14931513

申请日：2015-11-03

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G11C11/4076 ,  G06F3/06 ,  G06F5/06 ,  G06F1/08 ,  G11C7/10 ,  G06F13/16 ,  G06F12/06 ,  G11C11/409 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract translation: 描述了校准执行写操作所涉及的信号之间的时序关系的系统。 该系统包括耦合到一组存储器芯片的存储器控​​制器，其中每个存储器芯片包括相位检测器，该相位检测器被配置为在数据选通信号和存储器芯片之间从存储器控制器接收的时钟信号之间校准相位关系 一个写操作。 此外，存储器控制器被配置为执行一个或多个写入读取验证操作以校准数据选通信号和时钟信号之间的时钟周期关系，其中写入 - 读取验证操作涉及改变在 相对于时钟信号的数据选通信号乘以时钟周期的倍数。

公开(公告)号：US20170004866A1

公开(公告)日：2017-01-05

申请号：US15202773

申请日：2016-07-06

Applicant: Rambus Inc.

Inventor： Jade M. Kizer ,  Sivakumar Doraiswamy ,  Benedict Lau

IPC: G11C7/22 ,  G11C11/4063

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G06F13/405 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4063 ,  G11C11/4072 ,  G11C11/4096

Abstract: An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

Abstract translation: 公开了一种集成电路（IC）存储器控制器。 存储器控制器包括接收选通信号并提供内部选通信号的接收器。 可调延迟电路延迟使能信号以产生延迟使能信号。 门电路使用延迟的使能信号产生门控选通信号，该延迟使能信号掩蔽在内部选通信号的有效区域之前发生的内部选通信号的转变。 采样电路使用门控选通信号对数据进行采样。