公开(公告)号：US09405137B2

公开(公告)日：2016-08-02

申请号：US14283340

申请日：2014-05-21

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Robert Manouvrier

IPC: G02F1/025 ,  G02F1/225 ,  G02B6/12

CPC classification number: G02F1/025 ,  G02B6/12 ,  G02F1/2257 ,  H04B10/548

Abstract: A semiconductor electro-optical phase shifter may include an optical action zone configured to be inserted in an optical waveguide, and a bipolar transistor structure configured so that, in operation, collector current of the bipolar transistor structure crosses the optical action zone perpendicular to the axis of the optical waveguide.

公开(公告)号：US20160204031A1

公开(公告)日：2016-07-14

申请号：US15074130

申请日：2016-03-18

Applicant: STMicroelectronics SA

Inventor： Sylvain Joblot ,  Pierre Bar

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/66

CPC classification number: H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01P3/003 ,  H01P3/006 ,  H01P11/003 ,  H01L2924/00

Abstract: In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench.

公开(公告)号：US20160197048A1

公开(公告)日：2016-07-07

申请号：US15070046

申请日：2016-03-15

Applicant: STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Pierre Bar ,  Laurent Dussopt ,  Jean-Francois Carpentier

IPC: H01L23/66 ,  H01Q19/10 ,  H01L23/528 ,  H04B1/3827 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01Q13/10 ,  H01L23/522

CPC classification number: H01L23/66 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2924/15788 ,  H01Q1/243 ,  H01Q1/50 ,  H01Q9/0457 ,  H01Q13/106 ,  H01Q19/10 ,  H01Q23/00 ,  H04B1/3833 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941

Abstract: A three-dimensional integrated structure includes a support element, an interface device connected to the support element by a first electrically conductive connection, and an integrated circuit arranged between the support element and the interface device and connected to the interface device by a second electrically conductive connection. A filler region is positioned between the second electrically conductive connection and between the interface device and the integrated circuit. An antenna is distributed over the interface device and the integrated circuit and has a radiating element electromagnetically coupled with an excitation element through the interconnection of a slot.

Abstract translation: 三维集成结构包括支撑元件，通过第一导电连接连接到支撑元件的接口装置，以及布置在支撑元件和接口装置之间并且通过第二导电连接到接口装置的集成电路 连接。 填充区域位于第二导电连接之间以及接口装置和集成电路之间。 天线分布在接口装置和集成电路上，并且具有通过插槽的互连与激励元件电磁耦合的辐射元件。

公开(公告)号：US20160173036A1

公开(公告)日：2016-06-16

申请号：US14955969

申请日：2015-12-01

Applicant: STMicroelectronics SA

Inventor： Lionel Vogt ,  Baudouin Martineau ,  Aurelien Larie

IPC: H03F1/02 ,  H03F3/193 ,  H03F3/21

CPC classification number: H03F1/0205 ,  H03F1/0261 ,  H03F3/193 ,  H03F3/195 ,  H03F3/211 ,  H03F3/245 ,  H03F3/45179 ,  H03F2200/432 ,  H03F2200/451 ,  H03F2200/516 ,  H03F2203/21106 ,  H03F2203/45394

Abstract: An amplifier includes at least two amplification stages coupled in parallel. Each amplification stage includes at differential pair of amplifying MOS transistors having gates connected to a first and second input nodes common to amplifying stages, and bulk regions connected to each other but insulated from bulk regions of the amplifying MOS transistors of the other amplification stages. A configuration circuit generates bias voltage for application to the bulk terminals in each amplification stage to set the threshold voltages of the amplifying MOS transistors, and thus configuring the operating range of each amplification stage so that different amplification stages have different operating ranges.

Abstract translation: 放大器包括并联耦合的至少两个放大级。 每个放大级包括在具有连接到放大级共同的第一和第二输入节点的栅极的差分对放大MOS晶体管和彼此连接但与其它放大级的放大MOS晶体管的体区绝缘的体区域。 配置电路产生用于施加到每个放大级中的批量端子的偏压，以设置放大MOS晶体管的阈值电压，从而构成每个放大级的工作范围，使得不同的放大级具有不同的工作范围。

公开(公告)号：US20160172404A1

公开(公告)日：2016-06-16

申请号：US14840665

申请日：2015-08-31

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (Crolles 2) SAS

Inventor： Nayera Ahmed ,  Michel Marty

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14683 ,  H01L27/14687 ,  H01L27/14689

Abstract: An image sensor including a semiconductor layer; a stack of insulating layers resting on the back side of the semiconductor layer; a conductive layer portion extending along part of the height of the stack and flush with the exposed surface of the stack; laterally-insulated conductive fingers extending through the semiconductor layer from its front side and penetrating into said layer portion; laterally-insulated conductive walls separating pixel areas, these walls extending through the semiconductor layer from its front side and having a lower height than the fingers; and an interconnection structure resting on the front side of the semiconductor layer and including vias in contact with the fingers.

Abstract translation: 包括半导体层的图像传感器; 沉积在半导体层的背面上的一叠绝缘层; 导电层部分，其沿所述堆叠的高度的一部分延伸并与所述堆叠的暴露表面齐平; 横向绝缘的导电指状物从其前侧延伸穿过半导体层并且穿透到所述层部分中; 分隔像素区域的横向绝缘导电壁，这些壁从其前侧延伸穿过半导体层并且具有比手指低的高度; 以及搁置在半导体层的前侧上并且包括与手指接触的通孔的互连结构。

公开(公告)号：US20160164493A1

公开(公告)日：2016-06-09

申请号：US14847900

申请日：2015-09-08

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Thomas Quemerais ,  Alice Bossuet ,  Daniel Gloria

IPC: H03H11/24 ,  G01R1/067 ,  H03F3/60

CPC classification number: H03H11/245 ,  G01R1/06711 ,  H03F3/602 ,  H03F2200/211

Abstract: An attenuator includes: a first circuit including a common collector or common drain amplifier formed of a first transistor having its control node connected to an input of the attenuator and its emitter or source connected to an intermediate node of the attenuator; and a second circuit including a common collector or common drain amplifier formed of a second transistor having its emitter or source connected to the intermediate node and its control node connected to an output of the attenuator.

Abstract translation: 衰减器包括：第一电路，包括由第一晶体管形成的公共集电极或公共放电放大器，第一晶体管的控制节点连接到衰减器的输入，其发射极或源极连接到衰减器的中间节点; 以及第二电路，包括由其第二晶体管形成的公共集电极或公共漏极放大器，其第二晶体管的发射极或源极连接到中间节点，其控制节点连接到衰减器的输出。

公开(公告)号：US09354391B2

公开(公告)日：2016-05-31

申请号：US14494647

申请日：2014-09-24

Applicant: STMicroelectronics SA

Inventor： Pascal Fonteneau

IPC: G02B6/12 ,  G02B6/122 ,  H01L25/16 ,  H01L27/02 ,  H01L23/60 ,  H01L25/065 ,  H01L23/00

CPC classification number: G02B6/4275 ,  G02B6/122 ,  G02B6/428 ,  G02B2006/12061 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/60 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/167 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/87 ,  H01L2224/16235 ,  H01L2225/06534 ,  H01L2225/06572 ,  H01L2924/10253 ,  H01L2924/1431

Abstract: A device includes integrated circuit chips mounted on one another. At least one component for protecting elements of a second chip is formed in a first chip. The chips may be of the SOI type, with the first chip including a first SOI layer having a first thickness and the second chip including a second SOI layer having a second thickness smaller than the first thickness. The first chip including the component for protecting may include an optical waveguide with the component for protecting formed adjacent the optical waveguide.

Abstract translation: 一种装置包括彼此安装的集成电路芯片。 用于保护第二芯片的元件的至少一个部件形成在第一芯片中。 芯片可以是SOI型，其中第一芯片包括具有第一厚度的第一SOI层，第二芯片包括第二厚度小于第一厚度的第二SOI层。 包括用于保护的部件的第一芯片可以包括具有邻近光波导形成的用于保护的部件的光波导。

公开(公告)号：US20160105590A1

公开(公告)日：2016-04-14

申请号：US14848962

申请日：2015-09-09

Applicant: STMICROELECTRONICS SA

Inventor： Manu ALIBAY ,  Stéphane AUBERGER

IPC: H04N5/14 ,  H04N5/232

CPC classification number: H04N5/145 ,  G06T7/246 ,  G06T7/277 ,  G06T2207/10016 ,  H04N5/23254 ,  H04N5/23258 ,  H04N5/23277

Abstract: The method includes for each current pair of first and second successive video images determining movement between the two images. The determining includes a phase of testing homography model hypotheses on the movement by a RANSAC type algorithm operating on a set of points in the first image and first assumed corresponding points in the second image so as to deliver one of the homography model hypothesis that defines the movement. The test phase includes a test of first homography model hypotheses of the movement obtained from a set of second points in the first image and second assumed corresponding points in the second image. At least one second homography model hypothesis is obtained from auxiliary information supplied by an inertial sensor and representative of a movement of the image sensor between the captures of the two successive images of the pair.

Abstract translation: 该方法包括用于确定两个图像之间的移动的每对当前第一和第二连续视频图像对。 该确定包括通过对第一图像中的一组点和第二图像中的第一假定对应点操作的RANSAC类型算法来测试运动上的单应性模型假设的相位，以便递送定义 运动。 测试阶段包括从第一图像中的一组第二点和第二图像中的第二假定对应点获得的运动的第一单应性模型假设的测试。 从由惯性传感器提供的辅助信息获得至少一个第二单应性模型假说，并表示图像传感器在该对的两个连续图像的捕获之间的运动。

公开(公告)号：US20160099183A1

公开(公告)日：2016-04-07

申请号：US14965990

申请日：2015-12-11

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Denis Rideau ,  Elise Baylac ,  Emmanuel Richard ,  Francois Andrieu

IPC: H01L21/84 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/10

CPC classification number: H01L21/84 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/1218 ,  H01L27/1262 ,  H01L27/127 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78603

Abstract: The transverse mechanical stress within the active region of a MOS transistor is relaxed by forming an insulating incursion, such as an insulated trench, within the active region of the MOS transistor. The insulated incursion is provided at least in a channel region of the MOS transistor so as to separate the channel region into two parts. The insulated incursion is configured to extend in a direction of a length of the MOS transistor. The insulated incursion may further extend into one or more of a source region or drain region located adjacent the channel region of the MOS transistor.

公开(公告)号：US09305828B2

公开(公告)日：2016-04-05

申请号：US14526005

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Denis Rideau ,  Emmanuel Josse ,  Olivier Nier

IPC: H01L21/00 ,  H01L21/762 ,  H01L21/02 ,  H01L29/78 ,  H01L21/84 ,  H01L21/324

CPC classification number: H01L21/76283 ,  H01L21/02356 ,  H01L21/324 ,  H01L21/76237 ,  H01L21/84 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7847

Abstract: One or more embodiments of the invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a surface of a semiconductor structure having a stressed semiconductor layer and an insulator layer, at least two first trenches in a first direction delimiting a first dimension of at least one first transistor to be formed in the semiconductor structure; performing a first anneal to decrease the viscosity of the insulating layer; and forming, in the surface after the first anneal, at least two second trenches in a second direction delimiting a second dimension of the at least one transistor.

Abstract translation: 本发明的一个或多个实施方案涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层和绝缘体层的半导体结构的表面中形成至少两个第一方向的第一沟槽， 要在半导体结构中形成的至少一个第一晶体管的第一尺寸; 执行第一退火以降低绝缘层的粘度; 以及在所述第一退火之后的表面中，在限定所述至少一个晶体管的第二维度的第二方向上形成至少两个第二沟槽。