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公开(公告)号：US09734921B2
公开(公告)日：2017-08-15
申请号：US14407318
申请日：2013-10-31
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Suresh Rajan , Ian Shaeffer
CPC classification number: G11C29/4401 , G06F11/1016 , G06F11/1072 , G11C29/808 , G11C29/846
Abstract: A memory device (100) includes an extra column (114) of repair memory tiles. These repair memory tiles are accessed at the same time, and in the same manner as the main array of memory tiles. The output of the repair column is substituted for the output of a column of the main array (112). The main array column that is substituted is determined by tags (121) stored externally to the memory device. The external tags are queried with a partial address of the access. If the address of the access corresponds to an address in the external tags, the tag information is supplied to the memory device. The tag information determines which column in the main array is replaced by the output of the repair column. Since each column of the main array supplies one bit during the access, the repair column enables cell-by-cell replacement of main array cells.
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公开(公告)号：US09734357B2
公开(公告)日：2017-08-15
申请号：US14989155
申请日：2016-01-06
Applicant: Rambus Inc.
Inventor： Trung Am Diep , Pradeep Batra , Brian S. Leibowitz , Frederick A. Ware
IPC: G06F21/00 , G06F21/79 , G06F12/14 , H04L9/30 , G06F12/1009
CPC classification number: G06F21/79 , G06F12/1009 , G06F12/1408 , G06F2212/1052 , G06F2221/2107 , H04L9/30
Abstract: A memory controller encrypts contents of a page frame based at least in part on a frame key associated with the page frame. The memory controller generates a first encrypted version of the frame key based at least in part on a first process key associated with a first process, wherein the first encrypted version of the frame key is stored in a first memory table associated with the first process. The memory controller generates a second encrypted version of the frame key based at least in part on a second process key associated with a second process, wherein the second encrypted version of the frame key is stored in a second memory table associated with the second process, the first process and the second process sharing access to the page frame using the first encrypted version of the frame key and the second encrypted version of the frame key, respectively.
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公开(公告)号：US09667359B2
公开(公告)日：2017-05-30
申请号：US14718019
申请日：2015-05-20
Applicant: Rambus Inc.
Inventor： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
CPC classification number: H04B17/11 , H04B17/00 , H04B17/21 , H04L7/0004 , H04L7/0016 , H04L7/0087 , H04L7/043 , H04L7/10 , H04L27/00
Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.
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公开(公告)号：US09653146B2
公开(公告)日：2017-05-16
申请号：US14869294
申请日：2015-09-29
Applicant: RAMBUS INC.
Inventor： Frederick A. Ware , Suresh Rajan , Scott C. Best
IPC: G06F3/00 , G11C11/408 , G11C5/04 , G11C11/4093 , G06F12/06 , G06F13/16 , G11C7/10 , G11C7/22 , G11C11/4076
CPC classification number: G11C11/4082 , G06F12/06 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/1051 , G11C7/1078 , G11C7/22 , G11C11/4076 , G11C11/4093
Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.
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公开(公告)号：US20170110188A1
公开(公告)日：2017-04-20
申请号：US15338872
申请日：2016-10-31
Applicant: Rambus Inc.
Inventor： Deepak Chandra Sekar , Gary Bela Bronner , Frederick A. Ware
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C13/0097 , G11C2213/15 , G11C2213/72 , G11C2213/74 , G11C2213/75 , G11C2213/78 , G11C2213/79
Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.
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Patent Agency Ranking
公开(公告)号：US20170103029A1
公开(公告)日：2017-04-13
申请号：US15284307
申请日：2016-10-03
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Kenneth L. Wright
CPC classification number: G06F13/1684 , G06F11/073 , G06F11/0772 , G06F13/4027 , Y02D10/14 , Y02D10/151
Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.
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公开(公告)号：US20170097905A1
公开(公告)日：2017-04-06
申请号：US15333001
申请日：2016-10-24
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Amir Amirkhany , Suresh Rajan , Mohammad Hekmat , Dinesh Patil
CPC classification number: G06F13/1673 , G06F13/4068 , G11C5/02 , G11C7/10 , G11C7/1012 , G11C7/1021 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C8/18 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C11/419 , G11C29/022 , G11C29/023 , G11C29/028
Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
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公开(公告)号：US20170052845A1
公开(公告)日：2017-02-23
申请号：US15250677
申请日：2016-08-29
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Ely Tsern
CPC classification number: G06F11/1044 , G06F11/1048 , G06F11/1068 , G06F11/1666 , G06F11/20 , G11C7/10 , G11C29/42 , G11C29/4401 , G11C29/52 , G11C29/70 , G11C29/765 , G11C2029/4402 , H03M13/1575
Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.
Abstract translation: 公开了一种存储器模块，其包括衬底，输出读取数据的存储器件和缓冲器。 缓冲器具有用于将读取的数据传送到存储器控制器的主界面和耦合到存储器设备的辅助接口以接收读取的数据。 缓冲器包括用于识别所接收的读取数据中的错误并识别与该错误相关联的存储器件中的存储单元位置的错误逻辑。 修复逻辑将替换存储元素映射为与错误相关联的存储单元位置的替代存储元素。
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公开(公告)号：US20170052584A1
公开(公告)日：2017-02-23
申请号：US15248364
申请日：2016-08-26
Applicant: RAMBUS INC.
Inventor： Dinesh Patil , Amir Amirkhany , Farrukh Aquil , Kambiz Kaviani , Frederick A. Ware
CPC classification number: G06F1/324 , G06F1/3275 , G06F1/3287 , G06F5/065 , G06F2205/067 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C2207/2272 , H03L7/0816
Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
Abstract translation: 实施例通常涉及存储器件。 在一个实施例中，存储器件包括时钟接收器电路，其接收外部时钟信号并提供内部时钟信号。 存储装置还包括具有输入的延迟锁定环路电路（DLL）和接收内部时钟信号的电路。 该电路选择内部时钟信号的哪些脉冲被施加到DLL的输入端，使得从外部时钟信号的至少三个连续脉冲中选出的不超过两个时钟脉冲在预定的时间内被施加到DLL的输入 间隔。 在另一个实施例中，一种方法包括在时钟接收器电路处接收外部时钟信号，从时钟接收器电路接收内部时钟信号，以及选择内部时钟信号的哪些脉冲被施加到DLL的输入，其中不再有 从外部时钟信号的至少三个连续脉冲中选择的两个时钟脉冲在预定间隔期间被施加到DLL的输入端。
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公开(公告)号：US09515008B2
公开(公告)日：2016-12-06
申请号：US15019867
申请日：2016-02-09
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Ely Tsern , Thomas Vogelsang
IPC: H01L23/538 , H01L23/48 , H01L25/065 , H01L25/18 , G06F3/06
CPC classification number: H01L23/481 , G06F3/0604 , G06F3/0629 , G06F3/0673 , G06F2213/0038 , H01L25/0657 , H01L25/18 , H01L2224/131 , H01L2224/16146 , H01L2225/06544 , H01L2924/014
Abstract: An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes a core circuit located outside the contiguous region. The core circuit is coupled to at least one of the connection sites.
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