公开(公告)号：US20140003131A1

公开(公告)日：2014-01-02

申请号：US13860825

申请日：2013-04-11

Applicant: Frederick A. Ware ,  Lawrence Lai ,  Chad A. Bellows ,  Wayne S. Richardson

Inventor： Frederick A. Ware ,  Lawrence Lai ,  Chad A. Bellows ,  Wayne S. Richardson

IPC: G11C8/10

CPC classification number: G11C8/10 ,  G11C8/12 ,  G11C8/16

Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

Abstract translation: 存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。 集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。 在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。 在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。 响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。 第一和第二多个存储单元可以从该接口同时访问。

公开(公告)号：US08618869B2

公开(公告)日：2013-12-31

申请号：US13341483

申请日：2011-12-30

Applicant: Wayne Dettloff ,  John Wilson ,  Lei Luo ,  Brian Leibowitz ,  Jared Zerbe ,  Pravin Kumar Venkatesan

Inventor： Wayne Dettloff ,  John Wilson ,  Lei Luo ,  Brian Leibowitz ,  Jared Zerbe ,  Pravin Kumar Venkatesan

IPC: G05F1/10

CPC classification number: G06F1/26 ,  G06F1/3203 ,  H03K17/223

Abstract: Conventional bias circuits exhibit a number of limitations, including the time required to power-up a bias circuit following a low-power state. Large current surges in the supply network induce ringing, further complicating a power-up process. Example embodiments reduce power-up time and minimize current surges in the supply by selectively charging and discharging capacitance to the circuit during power-up and power-down of the bias circuit.

Abstract translation: 常规偏置电路表现出许多限制，包括在低功率状态之后上电偏置电路所需的时间。 供电网络中的大电流浪涌引起振铃，进一步使上电过程复杂化。 示例性实施例通过在偏置电路的加电和掉电期间选择性地对电路充电和放电电容来减小上电时间并最小化电源中的电流浪涌。

公开(公告)号：US20130346663A1

公开(公告)日：2013-12-26

申请号：US13747419

申请日：2013-01-22

Applicant: Rambus Inc.

Inventor： Stephen G. Tell

IPC: G06F13/38

CPC classification number: G06F1/26 ,  G06F1/10 ,  G06F12/0246 ,  G06F13/382 ,  G06F13/4072 ,  G06F2212/7201 ,  G11C7/1072 ,  H03K19/1776 ,  H04L7/02

Abstract: Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.

Abstract translation: 描述了一种用于控制在设备之间传输的信号的接口时序和/或电压操作的系统和方法。 处理器可以通过总线的一个或多个总线接口耦合到一个或多个对应的接口定时和/或电压比较电路以及对应的接口定时和/或电压调节电路。

公开(公告)号：US20130339464A1

公开(公告)日：2013-12-19

申请号：US13996443

申请日：2011-12-13

Applicant: Rouzbeh Moazami Goudarzi ,  John K. Thomas ,  Keith Thomas Sherry ,  Carl W. Werner

Inventor： Rouzbeh Moazami Goudarzi ,  John K. Thomas ,  Keith Thomas Sherry ,  Carl W. Werner

IPC: H04L29/06

CPC classification number: H04L65/1069 ,  H04L51/28 ,  H04L51/36 ,  H04L61/1547 ,  H04L67/14 ,  H04L67/306 ,  H04W8/18 ,  H04W76/15

Abstract: The present disclosure describes one embodiment of an operating center server for managing contact information and user identifiers of users who communicate with others using a plurality of different communication platforms that operate on disparate networks (e.g., a cellular network or a wireless local area network). The operating center server converges cellular connectivity services (e.g., cellular calls or SMS messages) with internet protocol (IP) services (e.g., email or VOIP calls) and provides these services to terminal devices regardless of the specific network connectivity available to the devices.

Abstract translation: 本公开描述了用于管理使用在不同网络（例如，蜂窝网络或无线局域网）上操作的多个不同通信平台与他人进行通信的联系人信息和用户标识符的操作中心服务器的一个实施例。 操作中心服务器将具有互联网协议（IP）服务（例如，电子邮件或VOIP呼叫）的蜂窝连接服务（例如，蜂窝呼叫或SMS消息）收敛，并将这些服务提供给终端设备，而不管设备可用的特定网络连接。

公开(公告)号：US20130336080A1

公开(公告)日：2013-12-19

申请号：US13884248

申请日：2011-11-10

Applicant: Yohan U. Frans ,  Wayne F. Ellis ,  Akash Bansal

Inventor： Yohan U. Frans ,  Wayne F. Ellis ,  Akash Bansal

IPC: H03L1/02

CPC classification number: G11C29/50012 ,  G01R23/02 ,  G01R23/15 ,  G01R35/005 ,  G06F1/08 ,  G06F1/12 ,  G06F11/1604 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/18 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H03L1/02

Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device.

公开(公告)号：US20130321022A1

公开(公告)日：2013-12-05

申请号：US13985364

申请日：2012-03-14

Applicant: Frederick A. Ware

Inventor： Frederick A. Ware

IPC: G01R31/26 ,  H03L7/00

CPC classification number: G01R31/2882 ,  G01R31/2607 ,  G01R31/31726 ,  G11C29/022 ,  G11C29/12015 ,  G11C29/16 ,  G11C29/50012 ,  G11C2029/0401 ,  H03L7/00

Abstract: A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.

Abstract translation: 半导体IC器件包括用于传送定时信号的定时电路，所述定时电路被配置为接收第一测试信号并且响应于所述第一测试信号而在定时信号中产生延迟，所述第一测试信号包括第一定时 事件。 所述半导体IC器件还包括接口电路，其被配置为响应于所述定时信号传送所述数据信号，所述接口电路还被配置为接收第二测试信号并响应于所述第二测试信号而实现所述数据信号的延迟 所述第二测试信号包括根据测试标准与所述第一定时事件相关的第二定时事件。

公开(公告)号：US08599631B2

公开(公告)日：2013-12-03

申请号：US12519908

申请日：2007-12-19

Applicant: Ian P. Shaeffer ,  Kyung S. Oh

Inventor： Ian P. Shaeffer ,  Kyung S. Oh

IPC: G11C7/00

CPC classification number: G11C7/22 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4063 ,  G11C11/4097 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028

Abstract: A system includes a plurality of memory devices arranged in a fly-by topology, each of the memory devices having on-die termination (ODT) circuitry for connection to an address and control (RQ) bus. The ODT circuitry has at least one input for controlling termination of one or more signal lines of the RQ bus. Application of a first logic level to the at least one input enables termination of the one or more signal lines. Application of a second logic level to the at least one input disables termination of the one or more signal lines.

Abstract translation: 系统包括以飞越拓扑布置的多个存储器件，每个存储器件具有用于连接到地址和控制（RQ）总线的片上终端（ODT）电路。 ODT电路具有用于控制RQ总线的一条或多条信号线的终止的至少一个输入。 将第一逻辑电平应用于所述至少一个输入使得能够终止所述一个或多个信号线。 将第二逻辑电平应用于至少一个输入禁止一个或多个信号线的终止。

公开(公告)号：US20130307607A1

公开(公告)日：2013-11-21

申请号：US13871193

申请日：2013-04-26

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh

IPC: H03K3/013

CPC classification number: H03K3/013 ,  G11C7/1084 ,  G11C7/1093 ,  G11C29/021 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H03K19/00346

Abstract: A data signal is transmitted from a first circuit to a second circuit, with noise and/or jitter added to the data signal by supply noise in the power distribution network in the first circuit and/or a second circuit being effectively canceled out by adjustment of the reference voltage and/or the phase of the sampling clock used for sampling of the data signal in a manner that effectively mimics such noise and/or jitter added to the data signal. The second circuit uses a filter that has the impedance profile and/or the jitter profile of such power distribution network. The bus weight and/or the number of switching bits in the data pattern transmitted from the first circuit to the second circuit is applied to the filter to determine the adjustment to be made to the reference voltage or the phase of the sampling clock.

Abstract translation: 数据信号从第一电路传输到第二电路，通过在第一电路中的配电网络中的电源噪声和/或第二电路中的噪声和/或抖动被添加到数据信号，通过调整 用于采样数据信号的采样时钟的参考电压和/或相位，以有效地模拟加到数据信号上的这种噪声和/或抖动。 第二电路使用具有这种配电网络的阻抗曲线和/或抖动曲线的滤波器。 将从第一电路发送到第二电路的数据模式中的总线权重和/或开关位数加到滤波器，以确定对参考电压或采样时钟的相位进行的调整。

公开(公告)号：US08588012B2

公开(公告)日：2013-11-19

申请号：US13149896

申请日：2011-06-01

Applicant: John Wilson ,  Joong-Ho Kim ,  Ravindranath Kollipara ,  David Secker ,  Kyung Suk Oh

Inventor： John Wilson ,  Joong-Ho Kim ,  Ravindranath Kollipara ,  David Secker ,  Kyung Suk Oh

IPC: G11C7/00

CPC classification number: G06F13/4086 ,  G06F13/4234

Abstract: Termination of a high-speed signaling link is effected by simultaneously engaging on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link.

Abstract translation: 高速信令链路的终止通过同时接合设置在同一存储器模块上的多个集成电路存储器件中的片上端接结构和/或在相同的集成电路封装内并且耦合到高速信号链路 信令链路。

公开(公告)号：US20130305074A1

公开(公告)日：2013-11-14

申请号：US13980826

申请日：2012-02-15

Applicant: Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G06F1/32

CPC classification number: G11C11/40615 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/022 ,  G11C29/028

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.