公开(公告)号：US20240319879A1

公开(公告)日：2024-09-26

申请号：US18736247

申请日：2024-06-06

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi ,  Bret Addison Johnson

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0679

Abstract: A device includes a first memory die and a second memory die directly coupled to the first memory die via a first bus. The device also includes a second bus directly coupled to the first memory die. The first memory die includes a first trim circuit that when in operation adjusts a delay of signal transmission by the first memory die to a first value, while the second memory die comprises a second trim circuit that when in operation adjusts a delay of signal transmission by the second memory die to a second value.

公开(公告)号：US12100476B2

公开(公告)日：2024-09-24

申请号：US17942944

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： Kari Crane ,  Kevin G. Werhane ,  Yoshinori Fujiwara ,  Jason M. Johnson ,  Takuya Tamano ,  Daniel S. Miller

IPC: G11C7/24 ,  G11C7/10 ,  G11C17/16

CPC classification number: G11C7/24 ,  G11C7/1039 ,  G11C7/1063 ,  G11C17/16

Abstract: An apparatus includes a TM control circuit that is configured to receive address information corresponding to a TM function and compare the address information with an authorized TM list stored in a memory of the apparatus to determine if there is a match. If there is a match, a latch load signal pulse is output. A TM latch circuit programs one or more latches based on the address information and based on the latch load signal pulse. The TM latch circuit decodes information in the one or more latches and, based on the decoded information, outputs a test mode signal to turn on test mode operations in circuits associated with the TM function. The apparatus includes a plurality of TM functions for testing various features of the apparatus and the authorized TM list identifies which of the plurality of TM functions has been authorized for customer use.

公开(公告)号：US12100467B2

公开(公告)日：2024-09-24

申请号：US17822032

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Yoshinori Fujiwara ,  Takuya Tamano ,  Jason M. Johnson ,  Kevin G. Werhane ,  Daniel S. Miller

IPC: G11C29/02 ,  G11C29/00 ,  G11C29/24 ,  G11C29/44 ,  G11C29/46

CPC classification number: G11C29/789 ,  G11C29/027 ,  G11C29/24 ,  G11C29/4401 ,  G11C29/46

Abstract: An electronic device includes multiple memory elements including multiple redundant memory elements. The electronic device also includes repair circuitry configured to remap data to the multiple memory elements when a failure occurs. The repair circuitry includes multiple fuse latches configured to implement the remapping. The repair circuitry also includes latch testing circuitry configured to test functionality of the multiple fuse latches. The latch testing circuitry includes selection circuitry configured to enable selection of a first set of fuse latches of the multiple fuse latches for a test separate from a second set of fuse latches of the multiple fuse latches that are unselected by the selection circuitry.

公开(公告)号：US12100454B2

公开(公告)日：2024-09-24

申请号：US17734623

申请日：2022-05-02

Applicant: Micron Technology, Inc.

Inventor： Jun Fujiki ,  Yoshiaki Fukuzumi ,  Akira Goda

IPC: G11C16/08 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/08 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, each of the tiers including memory cells and a control gate for the memory cells, each of the tiers including first transistors connected in series between the control gate in a respective tier and a conductive line, and second transistors connected in series between the control gate in the respective tier and the conductive line, the second transistors connected in parallel with the first transistors between the control gate and the conductive line, conductive joints coupled to channel regions of the first and second transistors, and gates for the first transistors and second transistors, each of the gates shared by one of the first transistors and one of the second transistors.

公开(公告)号：US12100439B2

公开(公告)日：2024-09-24

申请号：US17232986

申请日：2021-04-16

Applicant: Micron Technology, Inc.

Inventor： Takamasa Suzuki

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4099

CPC classification number: G11C11/4091 ,  G11C11/4087 ,  G11C11/4096 ,  G11C11/4099

Abstract: The present disclosure includes apparatuses and methods related to sensing operations in memory. An example apparatus can include an array of memory cells; and a controller coupled to the array configured to sense a first memory cell based upon a first input associated with the memory cell and a second input and a third input associated with a second memory cell.

公开(公告)号：US12099746B2

公开(公告)日：2024-09-24

申请号：US17116180

申请日：2020-12-09

Applicant: Micron Technology, Inc.

Inventor： Markus Balb ,  Thomas Hein ,  Heinz Hoenigschmid

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0679

Abstract: Methods, systems, and devices for interrupt signaling for a memory device are described. A memory device may transmit an interrupt signal to a host device to alter a sequence of operations that would otherwise be executed by the host device. The memory device may transmit the interrupt signal in response to detecting an error condition at the memory device, a performance degradation at the memory device, or another trigger event. In some examples, the memory device may include a dedicated interrupt pin for transmitting interrupt signals. Alternatively, the memory device may transmit interrupt signals via a pin also sued to transmit error detection codes. For example, the memory device may transmit an interrupt signal before or after an error detection code or may invert the error detection code to indicate the interrupt, in which case the inverted error detection code may act as an interrupt signal.

公开(公告)号：US20240315018A1

公开(公告)日：2024-09-19

申请号：US18676056

申请日：2024-05-28

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H10B41/35 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3215 ,  H01L21/67 ,  H01L21/768 ,  H10B20/00 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/35 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/3215 ,  H01L21/32155 ,  H01L21/67063 ,  H01L21/76802 ,  H10B20/383 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H01L2221/1063 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240315001A1

公开(公告)日：2024-09-19

申请号：US18598585

申请日：2024-03-07

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  David Daycock ,  Albert Liao ,  Si-Woo Lee ,  Haitao Liu

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/05

Abstract: Memory circuitry comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprising a transistor comprise a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A gate is operatively-proximate the channel region. A capacitor comprises a first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first and second capacitor electrodes. The first capacitor electrode is directly electrically coupled to the first source/drain region. The second capacitor electrode of multiple of the capacitors is directly electrically coupled with one another. Digitlines extend elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory-cell tiers are directly electrically coupled to individual of the digitlines. A wordline is in individual of the memory-cell tiers that comprises the gate of multiple of the individual transistors in the individual memory-cell tiers. The wordline in a lower of the memory-cell tiers has a greater minimum width than a minimum width of the wordline in a higher of the memory-cell tiers that is directly above the lower memory-cell tier. Methods are also disclosed.

公开(公告)号：US20240312554A1

公开(公告)日：2024-09-19

申请号：US18600360

申请日：2024-03-08

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Deping He ,  Zhongyuan Lu

IPC: G11C29/52 ,  G11C11/406 ,  G11C29/02

CPC classification number: G11C29/52 ,  G11C11/40622 ,  G11C29/022

Abstract: Methods, systems, and devices for efficient read disturb scanning are described. A memory system may limit a quantity of word lines scanned as part of a read disturb scan. For example, the memory system may select a threshold quantity of word lines of a block for the read disturb scan based on a characterization of the word lines, such as selecting one or more word lines having higher bit error rates than other word lines of the block. The memory system may perform the read disturb scan on the selected one or more word lines to determine respective failure bit counts of the selected word lines and exclude unselected word lines of the block from the read disturb scan. The memory system may determine whether to perform a refresh operation on the block based on whether a respective failure bit count satisfies a threshold failure bit count.

公开(公告)号：US20240312550A1

公开(公告)日：2024-09-19

申请号：US18598899

申请日：2024-03-07

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G11C29/42

CPC classification number: G11C29/42

Abstract: Per-row recent and/or baseline error information for word lines may be stored along the word lines in some examples. In some examples, baseline error information may be stored in a fuse array. In some examples, the baseline error information may be loaded from the fuse array to a memory array. In some examples, based on the recent and/or baseline error information, the memory device may provide a post-package repair recommendation.