公开(公告)号：US20120223738A1

公开(公告)日：2012-09-06

申请号：US13471009

申请日：2012-05-14

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk De Jong

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk De Jong

IPC: H03K19/177 ,  H01L21/78

CPC classification number: H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/36 ,  H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H03K19/177 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.

Abstract translation: 一种用于制造利用层转移的三维半导体器件的方法以及用于在预制半导体器件的顶部形成晶体管的步骤，所述预制半导体器件包括形成在晶体化半导体基底层上的晶体管和用于晶体管互连和绝缘层的金属层。 这种方法的优点是减少用于互连各种晶体管的所有金属长度。

公开(公告)号：US20120129301A1

公开(公告)日：2012-05-24

申请号：US13273712

申请日：2011-10-14

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Ze'ev Wurman ,  Paul Lim

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Ze'ev Wurman ,  Paul Lim

IPC: H01L21/822

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5252 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/16225 ,  H01L2924/00012

Abstract: A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

Abstract translation: 一种制造半导体器件的方法，所述方法包括：提供包括半导体区域的第一单晶层，将第一单晶层与隔离层重叠，转移包含半导体区域的第二单晶层覆盖隔离层，其中第一单晶层 并且第二单晶层由基本上不同的晶体材料形成; 随后蚀刻第二单晶层作为在第二单晶层中形成至少一个晶体管的一部分。

公开(公告)号：US20120091587A1

公开(公告)日：2012-04-19

申请号：US13251269

申请日：2011-10-02

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L23/522

CPC classification number: H01L21/76232 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/16 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1211 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/80006 ,  H01L2224/80009 ,  H01L2224/80047 ,  H01L2224/802 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01066 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00

Abstract: A 3D IC based system comprising a first semiconductor layer comprising first transistors, wherein the first transistors are interconnected by at least one metal layer comprising aluminum or copper; a second mono-crystallized semiconductor layer comprising second transistors and overlaying the metal layer; wherein the second mono-crystallized semiconductor layer thickness is less than 150 nm, and wherein at least one of the second transistors is an N-type transistor and at least one of the second transistors is a P-type transistor.

Abstract translation: 一种基于3D IC的系统，包括包括第一晶体管的第一半导体层，其中所述第一晶体管通过包括铝或铜的至少一个金属层互连; 第二单结晶半导体层，包括第二晶体管并覆盖所述金属层; 其中所述第二单结晶半导体层厚度小于150nm，并且其中所述第二晶体管中的至少一个为N型晶体管，并且所述第二晶体管中的至少一个为P型晶体管。

公开(公告)号：US08153499B2

公开(公告)日：2012-04-10

申请号：US13246391

申请日：2011-09-27

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/76

CPC classification number: G11C17/14 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11803 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K17/687 ,  H03K19/0948 ,  H03K19/17704 ,  H03K19/17756 ,  H03K19/17764 ,  H03K19/17796 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A method of manufacturing a semiconductor wafer, the method including: providing a base wafer including a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of the metal layers, wherein the monocrystalline layer includes second alignment marks; and performing a lithography using at least one of the first alignment marks and at least one of the second alignment marks.

Abstract translation: 一种制造半导体晶片的方法，所述方法包括：提供包括半导体衬底，金属层和第一对准标记的基底晶片; 在所述金属层的顶部上转移单晶层，其中所述单晶层包括第二对准标记; 以及使用所述第一对准标记和所述第二对准标记中的至少一个来执行光刻。

公开(公告)号：US20120032294A1

公开(公告)日：2012-02-09

申请号：US13162154

申请日：2011-06-16

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar

IPC: H01L27/04

CPC classification number: H01L27/08 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/80001

Abstract: A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.

Abstract translation: 一种半导体器件，包括：第一单晶硅层，包括第一晶体管，第一对准标记和覆盖所述第一单晶硅层的至少一个金属层，其中所述至少一个金属层比其它材料包含铜或铝; 覆盖所述至少一个金属层的第二层，所述第二层包括第二晶体管，第二对准标记和穿过所述第二层的通孔，其中所述通孔是所述第一晶体管和所述第二晶体管之间的连接路径的一部分 ，其中所述通孔的对准基于所述第一对准标记和所述第二对准标记，并且受到所述第一对准标记和所述第二对准标记之间的距离的影响。

公开(公告)号：US20120012895A1

公开(公告)日：2012-01-19

申请号：US13246384

申请日：2011-09-27

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar ,  Zeev Wurman

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar ,  Zeev Wurman

IPC: H01L27/118

CPC classification number: H01L27/0688 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/268 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/367 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66272 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66848 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/78639 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/808 ,  H01L29/812 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2924/00012 ,  H01L2924/01015

Abstract: A system includes a semiconductor device. The semiconductor device includes a first semiconductor layer comprising first transistors, wherein the first transistors are interconnected by at least one metal layer comprising aluminum or copper. The second mono-crystallized semiconductor layer includes second transistors and is overlaying the at least one metal layer, wherein the second mono-crystallized semiconductor layer is less than 150 nm in thickness, and at least one of the second transistors is an N-type transistor and at least one of the second transistors is a P-type transistor.

Abstract translation: 系统包括半导体器件。 该半导体器件包括包括第一晶体管的第一半导体层，其中第一晶体管通过包括铝或铜的至少一个金属层互连。 第二单结晶半导体层包括第二晶体管并且覆盖至少一个金属层，其中第二单结晶半导体层的厚度小于150nm，并且至少一个第二晶体管是N型晶体管 并且所述第二晶体管中的至少一个是P型晶体管。

公开(公告)号：US20110233676A1

公开(公告)日：2011-09-29

申请号：US13073268

申请日：2011-03-28

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

IPC: H01L27/12

CPC classification number: H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/36 ,  H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H03K19/177 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.

公开(公告)号：US20110233617A1

公开(公告)日：2011-09-29

申请号：US13073188

申请日：2011-03-28

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

IPC: H01L27/08

CPC classification number: H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/36 ,  H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H03K19/177 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.

Abstract translation: 一种用于制造利用层转移的三维半导体器件的方法以及用于在预制半导体器件的顶部形成晶体管的步骤，所述预制半导体器件包括形成在晶体化半导体基底层上的晶体管和用于晶体管互连和绝缘层的金属层。 这种方法的优点是减少用于互连各种晶体管的所有金属长度。

公开(公告)号：US07964916B2

公开(公告)日：2011-06-21

申请号：US12792673

申请日：2010-06-02

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan L. de Jong ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan L. de Jong ,  Deepak C. Sekar

IPC: H01L27/12

CPC classification number: H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/36 ,  H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/3011 ,  H03K19/177 ,  H03K19/17704 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.

Abstract translation: 一种用于制造利用层转移的三维半导体器件的方法以及用于在预制半导体器件的顶部形成晶体管的步骤，所述预制半导体器件包括形成在晶体化半导体基底层上的晶体管和用于晶体管互连和绝缘层的金属层。 这种方法的优点是减少用于互连各种晶体管的所有金属长度。

公开(公告)号：US20100295136A1

公开(公告)日：2010-11-25

申请号：US12792673

申请日：2010-06-02

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  J. L. de Jong ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  J. L. de Jong ,  Deepak C. Sekar

IPC: H01L27/08

CPC classification number: H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/36 ,  H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/3011 ,  H03K19/177 ,  H03K19/17704 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.

Abstract translation: 一种用于制造利用层转移的三维半导体器件的方法以及用于在预制半导体器件的顶部形成晶体管的步骤，所述预制半导体器件包括形成在晶体化半导体基底层上的晶体管和用于晶体管互连和绝缘层的金属层。 这种方法的优点是减少用于互连各种晶体管的所有金属长度。