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    Liquid crystal display apparatus
    41.
    发明授权
    Liquid crystal display apparatus 有权
    液晶显示装置

    公开(公告)号：US07522145B2

    公开(公告)日：2009-04-21

    申请号：US10183129

    申请日：2002-06-26

    Applicant: Dong-Ho Lee ,  Jin Jeon

    Inventor： Dong-Ho Lee ,  Jin Jeon

    IPC: G09G3/36

    CPC classification number: G11C19/28 ,  G02F1/1345 ,  G02F2001/13456 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2310/0281 ,  G11C8/04 ,  G11C19/00 ,  G11C19/184

    Abstract: A liquid crystal display apparatus is disclosed. A plurality of pixel electrodes are arranged on a display region of a substrate in a matrix form having a plurality of column lines and a plurality of row lines. Each of a plurality of thin film transistors has a first current electrode connected to a corresponding one of the plurality of pixel electrodes. Each of a plurality of data lines is arranged between odd column line and even column line of a pair of the plurality of column lines and is connected to second current electrodes of thin film transistors which are coupled to odd column line and even column line of the pair. Each of a plurality of first gate lines is connected to gate electrodes of odd thin film transistors which are coupled to one of the plurality of row lines. Each of a plurality of second gate lines is connected to gate electrodes of even thin film transistors which is coupled to the one of the plurality of row lines. A data driving circuit is provided for driving the data lines. At least two gate driving circuits having a first gate driving circuit and a second gate driving circuit are provided, wherein the first gate driving circuit is connected to the plurality of first gate lines and the second gate driving circuit is connected to the plurality of second gate lines.

    Abstract translation: 公开了一种液晶显示装置。 多个像素电极以具有多个列线和多条行线的矩阵形式布置在基板的显示区域上。 多个薄膜晶体管中的每一个具有连接到多个像素电极中对应的一个像素电极的第一电流电极。 多条数据线中的每条数据线被布置在多条列线对中的奇数列线和偶数列线之间，并连接到薄膜晶体管的第二电流电极，薄膜晶体管耦合到奇数列线和偶数列线 对。 多个第一栅极线中的每一个连接到耦合到多个行线之一的奇数薄膜晶体管的栅电极。 多个第二栅极线中的每一个连接到耦合到多个行线中的一个的偶数薄膜晶体管的栅电极。 提供数据驱动电路用于驱动数据线。 提供具有第一栅极驱动电路和第二栅极驱动电路的至少两个栅极驱动电路，其中第一栅极驱动电路连接到多个第一栅极线，第二栅极驱动电路连接到多个第二栅极 线条。

    Method of forming source/drain region of semiconductor device
    47.
    发明授权
    Method of forming source/drain region of semiconductor device 有权
    形成半导体器件的源极/漏极区域的方法

    公开(公告)号：US07312113B2

    公开(公告)日：2007-12-25

    申请号：US11399877

    申请日：2006-04-07

    Applicant: Dong Ho Lee

    Inventor： Dong Ho Lee

    IPC: H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L21/823814

    Abstract: A method of forming a source/drain region of a semiconductor device includes forming a photoresist pattern through which an NMOS region of a semiconductor substrate is exposed, and then performing an ion implant process to form NMOS LDD regions in the semiconductor substrate of the NMOS region. An ion implant process is performed to form PMOS pocket regions in a PMOS region of the semiconductor substrate. Spacers are formed on sidewalls of a PMOS gate electrode pattern and sidewalls of an NMOS gate electrode pattern, and an ion implant process is performed to form PMOS source/drain regions in the semiconductor substrate in which the PMOS pocket regions are formed. An ion implant process is performed to form NMOS source/drain regions in the semiconductor substrate in which the NMOS LDD regions are formed.

    Abstract translation: 形成半导体器件的源极/漏极区域的方法包括形成通过其暴露半导体衬底的NMOS区域的光致抗蚀剂图案，然后进行离子注入工艺以在NMOS区域的半导体衬底中形成NMOS LDD区域 。 执行离子注入工艺以在半导体衬底的PMOS区域中形成PMOS袋区域。 间隔件形成在PMOS栅电极图案的侧壁和NMOS栅电极图案的侧壁上，并且执行离子注入工艺以在其中形成PMOS袋区域的半导体衬底中形成PMOS源/漏区。 执行离子注入工艺以在其中形成NMOS LDD区的半导体衬底中形成NMOS源极/漏极区。

    STACK-TYPE SEMICONDUCTOR DEVICE HAVING COOLING PATH ON ITS BOTTOM SURFACE
    48.
    发明申请
    STACK-TYPE SEMICONDUCTOR DEVICE HAVING COOLING PATH ON ITS BOTTOM SURFACE 有权
    具有底部表面冷却路径的堆叠型半导体器件

    公开(公告)号：US20070267738A1

    公开(公告)日：2007-11-22

    申请号：US11751464

    申请日：2007-05-21

    Applicant: Hyun-Soo CHUNG ,  Cha-Jea JO ,  Dong-Ho LEE ,  Seong-Deok HWANG

    Inventor： Hyun-Soo CHUNG ,  Cha-Jea JO ,  Dong-Ho LEE ,  Seong-Deok HWANG

    IPC: H01L23/34 ,  H01L21/00

    CPC classification number: H01L23/473 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/10158 ,  H01L2924/00

    Abstract: Provided is a semiconductor device having a cooling path on its bottom surface. The stack-type semiconductor device having a cooling path comprises a stack-type semiconductor chip comprising a first semiconductor chip and a second semiconductor chip. The first semiconductor chip comprises a first surface in which a circuit unit is formed and a second surface in which a first cooling path is formed, and the second semiconductor chip comprises a first surface in which a circuit unit is formed and a second surface in which a second cooling path is formed. The second surface of the first semiconductor chip and the second surface of the second semiconductor chip are bonded to each other, and a third cooling path is formed in the middle of the stack-type semiconductor chip using the first and second cooling paths. Warpage of the stack-type semiconductor device is suppressed and heat is easily dissipated.

    Abstract translation: 提供了在其底面上具有冷却路径的半导体器件。 具有冷却路径的叠层型半导体器件包括：堆叠型半导体芯片，包括第一半导体芯片和第二半导体芯片。 第一半导体芯片包括其中形成有电路单元的第一表面和形成有第一冷却路径的第二表面，并且第二半导体芯片包括其中形成电路单元的第一表面和第二表面，其中第二表面 形成第二冷却路径。 第一半导体芯片的第二表面和第二半导体芯片的第二表面彼此接合，并且使用第一和第二冷却路径在堆叠型半导体芯片的中间形成第三冷却路径。 堆叠型半导体器件的翘曲被抑制，并且易于散热。

    Multi-chip package for reducing parasitic load of pin
    49.
    发明申请
    Multi-chip package for reducing parasitic load of pin 有权
    用于减少引脚寄生负载的多芯片封装

    公开(公告)号：US20070228546A1

    公开(公告)日：2007-10-04

    申请号：US11797592

    申请日：2007-05-04

    Applicant: Byung-Se So ,  Dong-Ho Lee

    Inventor： Byung-Se So ,  Dong-Ho Lee

    IPC: H01L23/52

    CPC classification number: H01L25/0657 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01025 ,  H01L2924/01055 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/05099

    Abstract: A multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The input/output pad of the first semiconductor chip directly receives an input/output signal via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed.

    Abstract translation: 多芯片封装包括第一至第N个半导体芯片，每个半导体芯片包括输入/​​输出焊盘，耦合到输入/输出焊盘的输入/输出驱动器和内部电路。 第一至第N半导体芯片中的每一个包括用于耦合内部输入/输出驱动器和内部电路的内部焊盘。 第一半导体芯片的输入/输出焊盘通过多芯片封装的相应引脚直接接收输入/输出信号。 第二至第N半导体芯片通过彼此耦合的内部焊盘间接接收输入/输出信号。 当信号以高速传输到引脚时，多芯片封装可以通过将引脚的寄生负载保持在至少单个芯片的电平来提高信号兼容性。

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