摘要:
Provided are a wafer level chip scale package in which a redistribution process is applied at a wafer level, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package. The wafer level chip scale package includes a semiconductor chip having a bonding pad, a first insulating layer disposed on the semiconductor chip so as to expose the bonding pad, a redistribution line disposed on the exposed bonding pad and the first insulating layer, a sacrificial layer disposed below a redistribution pad of the redistribution line, a second insulating layer disposed on the redistribution line so as to expose the redistribution pad and including a crack inducement hole disposed beside the sacrificial layer, and an external connection terminal attached to the redistribution pad.
摘要:
A semiconductor device having a through electrode and a method of fabricating the same are disclosed. In one embodiment, a semiconductor device includes a first insulating layer formed on a semiconductor substrate. A wiring layer having a first aperture to expose a portion of the first insulating layer is formed on the first insulating layer. A second insulating layer is formed on an upper portion of the wiring layer and in the first aperture. A conductive pad having a second aperture to expose a portion of the second insulating layer is formed on the second insulating layer. A through hole with a width narrower than widths of the first and second apertures is formed through the first and second insulating layers and an upper portion of the semiconductor substrate. A through electrode is formed in the through hole.
摘要:
A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.
摘要:
Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages.
摘要:
Provided is a stack-type semiconductor package including a base chip having a circuit formed on one of its surfaces, at least one stack chip having a circuit stacked on the base chip, an adhesive interposed between the base chip and the stack chip, and signal transmission members formed along a lateral surface of the stack chip. The fabrication process of this stack-type semiconductor package may be simplified and the number of process operations may be lessened, thereby reducing the production time and cost. Also, a state of electrical contact of a terminal with a signal transmission member may be solidified, thereby improving the reliability of the stack-type semiconductor package. Furthermore, new post-type signal transmission members are adopted instead of wires or electrodes so that the structural stability and productivity of the stack-type semiconductor package may be markedly enhanced.
摘要:
Provided are a method of forming a metal layer wiring structure on the backside of a wafer, a metal layer wiring structure formed using the method, a method of stacking a chip package, and a chip package stack structure formed using the method. The method of stacking a chip package includes: forming recess patterns on a backside of wafers; forming a passivation layer on the backside of the wafers except for an area corresponding to a through electrode; forming a metal layer on the passivation layer; planarizing the metal layers to expose only the recess patterns; forming a lower insulating layer on the planarized metal layers except for an area corresponding to a contact portion with another wafer; forming an adhesive layer on the lower insulating layer of each of the wafers; and adhering the wafers to one another, wherein the recess patterns are formed using a laser.
摘要:
Disclosed is a magnesium alloy that has high thermal conductivity and flame retardancy and facilitates plastic working, wherein magnesium is added with 0.5 to 5 wt % of zinc and 0.6 to 3.5 wt % of tin (Sn) as a high-melting-point oxide-film-forming element, with, as necessary, 1.5 wt % or less of at least one selected from among calcium (Ca), silicon (Si), manganese (Mn) and mischmetal, the total amount of alloy elements being 2.5 to 6.3 wt %. A method of manufacturing the same is also provided, including melting high-melting-point alloy elements in the form of a master alloy in a magnesium—zinc alloy melt, followed by casting, removing a chill from the cast material, diffusion annealing, and then molding through a tempering process such as rolling, extrusion or forging. This magnesium alloy is improved in ductility by the action of alloy elements for inhibiting the formation of plate-like precipitates in a magnesium matrix structure, can be extruded even at a pressure of 1,000 kgf/cm2 or less due to the increased plasticity thereof, and can exhibit thermal conductivity of 100 W/m·K or more and flame retardancy satisfying the requirements for aircraft materials and is thus suitable for use in fields requiring fire safety, thereby realizing wide application thereof as a heat sink or a structural material for portable appliances, vehicles and aircraft components and contributing to weight reduction.
摘要:
Disclosed is a magnesium alloy that has high thermal conductivity and flame retardancy and facilitates plastic working, wherein magnesium is added with 0.5 to 5 wt % of zinc (Zn) and 0.3 to 2.0 wt % of at least one of yttrium (Y) and mischmetal, with, as necessary, 1.0 wt % or less of at least one selected from among calcium (Ca), silicon (Si), manganese (Mn) and tin (Sn), the total amount of alloy elements being 2.5 to 6 wt %. A method of manufacturing the same is also provided, including preparing a magnesium-zinc alloy melt in a melting furnace, adding high-melting-point elements in the form of a master alloy and melting them, and performing mechanical stirring during cooling of a cast material in a continuous casting mold containing the magnesium alloy melt, thus producing a magnesium alloy cast material having low segregation, after which a chill is removed from the cast material or diffusion annealing is performed, followed by molding through a tempering process such as rolling, extrusion or forging. This magnesium alloy is improved in ductility by the action of alloy elements for inhibiting the formation of lamella precipitates due to a low-melting-point eutectic phase in a magnesium matrix structure, can be extruded even at a pressure of 1,000 kgf/cm2 or less due to the increased plasticity thereof, and can exhibit thermal conductivity of 100 W/m·K or more and flame retardancy satisfying the requirements for aircraft materials and is thus suitable for use in fields requiring fire safety, thereby realizing wide application thereof as a heat sink or a structural material for portable appliances, vehicles and aircraft components and contributing to weight reduction.
摘要:
An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal, an input/output (I/O) pad, where the I/O pad includes a first portion in contact with the terminal and a second portion that extends over the passivation layer, and an electroless plating layer disposed on the I/O pad.
摘要翻译:互连结构包括具有内部电路的集成电路(IC)芯片和用于将内部电路电连接到外部电路的端子,设置在IC芯片的顶表面上的钝化层,该钝化层被配置为保护内部电路 以及使所述终端暴露于所述I / O焊盘包括与所述端子接触的第一部分和在所述钝化层上延伸的第二部分的输入/输出(I / O)焊盘,以及设置在所述钝化层上的无电镀层 I / O板。
摘要:
A semiconductor package comprises a substrate having a first opening formed therethrough, a first semiconductor chip stacked on the substrate in a flip chip manner and having a second opening formed therethrough, a second semiconductor chip stacked on the first semiconductor chip in a flip chip manner and having a third opening formed therethrough, and a molding material covering the first semiconductor chip and the second semiconductor chip and filling up a space between the substrate and the first semiconductor chip, a space between the first semiconductor chip and the second semiconductor chip, and filling each of the first opening, the second opening, and the third opening.