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12 条记录 (耗时 0.03 秒)

    SEMICONDUCTOR MEMORY DEVICE WITH HIERARCHICAL BIT LINE STRUCTURE
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE WITH HIERARCHICAL BIT LINE STRUCTURE 有权

    公开(公告)号：US20090154213A1

    公开(公告)日：2009-06-18

    申请号：US12347233

    申请日：2008-12-31

    申请人： Nam-Seog KIM ,  Jong-Cheol LEE ,  Hak-Soo YU ,  Uk-Rae CHO

    发明人： Nam-Seog KIM ,  Jong-Cheol LEE ,  Hak-Soo YU ,  Uk-Rae CHO

    IPC分类号： G11C5/02 ,  G11C8/00 ,  G11C7/06 ,  G11C5/06

    CPC分类号： G11C11/417 ,  G11C7/18 ,  G11C8/12

    摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

    AMPLIFIER CIRCUIT HAVING CONSTANT OUTPUT SWING RANGE AND STABLE DELAY TIME
    9.
    发明申请
    AMPLIFIER CIRCUIT HAVING CONSTANT OUTPUT SWING RANGE AND STABLE DELAY TIME 失效
    具有恒定输出振荡范围和稳定延迟时间的放大器电路

    公开(公告)号：US20070139084A1

    公开(公告)日：2007-06-21

    申请号：US11627794

    申请日：2007-01-26

    申请人： Nam-Seog KIM ,  Yong-Jin Yoon ,  Uk-Rae Cho

    发明人： Nam-Seog KIM ,  Yong-Jin Yoon ,  Uk-Rae Cho

    IPC分类号： H03K5/22

    CPC分类号： H03K3/356139

    摘要： Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal reference signal with a predetermined voltage level and maintains constant the amount of a first current, and the second bias unit receives an external reference signal, responds to a control voltage, and controls the amount of a second current to be the same as the amount of the first current, and the comparison unit compares a voltage level of a first node with a voltage level of a second node, and controls a voltage level of the control voltage according to the comparison result, and the amplifier unit compares a voltage level of an external input signal with a voltage level of the external reference signal, amplifies and outputs a voltage difference between the two compared signals, responds to the control voltage, and controls the amount of a third current to be the same as the amount of the first current although the level of the external reference signal is varied, such that the amplifier circuit and a circuit for receiving data can maintain a constant output swing range and a stable delay time irrespective of variations in the voltage levels of the external input signal or the external reference signal.

    摘要翻译： 提供了具有恒定的输出摆幅范围和稳定延迟时间的放大器电路，其中放大器电路包括第一偏置单元，第二偏置单元，比较单元和放大器单元，并且第一偏置单元响应内部 具有预定电压电平的参考信号并且保持第一电流的量的恒定，并且第二偏置单元接收外部参考信号，响应于控制电压，并且将第二电流的量控制为与第 第一电流和比较单元将第一节点的电压电平与第二节点的电压电平进行比较，并且根据比较结果控制控制电压的电压电平，并且放大器单元将电压电平 具有外部参考信号电压电平的外部输入信号，放大并输出两个比较信号之间的电压差，响应控制电压，并控制 尽管外部参考信号的电平变化，但是第三电流的量与第一电流的量相同，使得放大器电路和用于接收数据的电路可以保持恒定的输出摆幅范围和稳定的 延迟时间，而不管外部输入信号或外部参考信号的电压电平的变化。

    SEMICONDUCTOR MEMORY DEVICE WITH HIERARCHICAL BIT LINE STRUCTURE
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE WITH HIERARCHICAL BIT LINE STRUCTURE 有权
    具有分层位线结构的半导体存储器件

    公开(公告)号：US20090154265A1

    公开(公告)日：2009-06-18

    申请号：US12347239

    申请日：2008-12-31

    申请人： Nam-Seog KIM ,  Jong-Cheol LEE ,  Hak-Soo YU ,  Uk-Rae CHO

    发明人： Nam-Seog KIM ,  Jong-Cheol LEE ,  Hak-Soo YU ,  Uk-Rae CHO

    IPC分类号： G11C11/416 ,  G11C8/00

    CPC分类号： G11C11/417 ,  G11C7/18 ,  G11C8/12

    摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

    摘要翻译： 半导体存储器件具有分层位线结构。 半导体存储器件可以包括第一和第二存储器单元簇，其共享相同的位线对并且在操作上被分割; 第三和第四存储单元簇，其分别对应于与第一和第二存储器单元簇耦合的字线，并且共享与位线对不同的位线对，并在操作上分割; 以及用于响应于列选择信号将与第一至第四存储器单元簇连接的位线对之一切换到公共读出放大器的列通路。 由此，连接到位线的外围电路的负载导致的工作速度降低得到改善，并且随着芯片尺寸的减小，列通道的数量大幅减少。