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    Semiconductor memory structures
    44.
    发明授权
    Semiconductor memory structures 有权
    半导体存储器结构

    公开(公告)号：US08410607B2

    公开(公告)日：2013-04-02

    申请号：US11763938

    申请日：2007-06-15

    Applicant: Shau-Lin Shue ,  Chao-An Jong

    Inventor： Shau-Lin Shue ,  Chao-An Jong

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H01L45/144 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1683 ,  H01L45/1691

    Abstract: A semiconductor structure includes a transistor over a substrate, the transistor comprising a gate and a contact region, which is adjacent to the gate and within the substrate. A first dielectric layer is over the contact region. A contact structure is within the first dielectric layer and over the contact region. A first electrode and a second electrode are within the first dielectric layer, wherein at least one of the first electrode and the second electrode is over the contact structure. The first electrode and second electrodes may be laterally or vertically separated. A phase change structure is disposed between the first electrode and the second electrode. The phase change structure includes at least one spacer within the first dielectric layer and a phase change material (PCM) layer over the spacer.

    Abstract translation: 半导体结构包括在衬底上的晶体管，所述晶体管包括与栅极和衬底内的栅极和接触区域。 第一电介质层在接触区域之上。 接触结构在第一介电层内部和接触区域之上。 第一电极和第二电极在第一电介质层内，其中第一电极和第二电极中的至少一个位于接触结构之上。 第一电极和第二电极可以是横向或垂直分离的。 相变结构设置在第一电极和第二电极之间。 相变结构包括第一介电层内的至少一个间隔物和间隔物上的相变材料（PCM）层。

    DIELECTRIC PROTECTION LAYER AS A CHEMICAL-MECHANICAL POLISHING STOP LAYER
    47.
    发明申请
    DIELECTRIC PROTECTION LAYER AS A CHEMICAL-MECHANICAL POLISHING STOP LAYER 有权
    电介质保护层作为化学机械抛光停止层

    公开(公告)号：US20120205814A1

    公开(公告)日：2012-08-16

    申请号：US13028889

    申请日：2011-02-16

    Applicant: Yung-Hsu WU ,  Hsin-Hsien LU ,  Tien-I BAO ,  Shau-Lin SHUE

    Inventor： Yung-Hsu WU ,  Hsin-Hsien LU ,  Tien-I BAO ,  Shau-Lin SHUE

    IPC: H01L23/48 ,  H01L21/768

    CPC classification number: H01L21/3212 ,  H01L21/02203 ,  H01L21/02348 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/7684 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The disclosure provides mechanisms of performing metal chemical-mechanical polishing (CMP) without significant loss of copper and a dielectric film of damascene structures. The mechanisms use a metal CMP stop layer made of a low-k dielectric film with a porogen, which significantly reduces the removal rate of the metal CMP stop layer by metal CMP. The metal CMP stop layer is converted into a porous low-k dielectric film after a cure (or curing) to remove or convert the porogen. The low-k value, such as equal to or less than about 2.6, of the metal CMP stop layer makes the impact of using of the metal CMP stop layer on RC delay from minimum to none. Further the CMP stop layer protects the porous low-k dielectric film underneath from exposure to water, organic compounds, and mobile ions in the CMP slurry.

    Abstract translation: 本公开提供了进行金属化学机械抛光（CMP）而不显着损失铜和镶嵌结构的介电膜的机理。 这些机制使用由具有致孔剂的低k电介质膜制成的金属CMP停止层，这显着地降低了通过金属CMP的金属CMP停止层的去除速率。 在固化（或固化）之后，将金属CMP停止层转化为多孔低k电介质膜以去除或转化致孔剂。 金属CMP停止层的低k值（例如等于或小于约2.6）使得金属CMP停止层的使用对RC延迟的影响从最小到无。 此外，CMP停止层保护下面的多孔低k电介质膜不暴露于CMP浆料中的水，有机化合物和移动离子。

    Low resistance high reliability contact via and metal line structure for semiconductor device
    49.
    发明授权
    Low resistance high reliability contact via and metal line structure for semiconductor device 有权
    低电阻高可靠性接触通孔和半导体器件的金属线结构

    公开(公告)号：US08106512B2

    公开(公告)日：2012-01-31

    申请号：US12845852

    申请日：2010-07-29

    Applicant: Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

    Inventor： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H01L23/53238 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer.

    Abstract translation: 上述结构和方法提供了提高互连可靠性和电阻率的机制。 通过使用复合阻挡层来提高互连的可靠性和电阻率，该复合阻挡层提供良好的台阶覆盖率，良好的铜扩散阻挡层和与相邻层的良好粘附性。 复合阻挡层包括ALD阻挡层以提供良好的阶梯覆盖。 复合阻挡层还包括至少包含含有Mn，Cr，V，Ti或Nb的元素或化合物以提高粘合性的阻隔增粘膜。 复合阻挡层还可以包括在ALD阻挡层和阻挡增粘层之间的Ta或Ti层。

    Apparatus for Electrochemical Plating Semiconductor Wafers
    50.
    发明申请
    Apparatus for Electrochemical Plating Semiconductor Wafers 有权
    电化学电镀半导体晶片的装置

    公开(公告)号：US20110259734A1

    公开(公告)日：2011-10-27

    申请号：US13176839

    申请日：2011-07-06

    Applicant: Chung-Liang Chang ,  Shau-Lin Shue

    Inventor： Chung-Liang Chang ,  Shau-Lin Shue

    IPC: C25D7/12 ,  C25D17/06 ,  C25D17/10 ,  C25D17/02

    CPC classification number: H01L21/2885 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/007 ,  H01L21/76877

    Abstract: An electroplating apparatus for depositing a conductive material on a semiconductor wafer includes a vessel for holding an electroplating bath, a support for holding a semiconductor wafer within the vessel and beneath a surface of the bath; first and second electrodes within the vessel, between which an electrical current may flow causing conductive material to be electrolytically deposited onto the wafer, a third electrode disposed outside of the bath for applying a static electric charge to the wafer, and an electrical power supply coupled with the third electrode.

    Abstract translation: 用于在半导体晶片上沉积导电材料的电镀设备包括用于保持电镀槽的容器，用于将半导体晶片保持在容器内并在浴表面下方的支撑体; 容器内的第一和第二电极，电流可以在其间流动，导致导电材料被电解沉积到晶片上;第三电极，设置在电镀槽的外面，用于向晶片施加静电荷;以及电源， 与第三电极。

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