公开(公告)号：US20200176475A1

公开(公告)日：2020-06-04

申请号：US16786828

申请日：2020-02-10

申请人： SUNRISE MEMORY CORPORATION

发明人： Eli Harari

IPC分类号： H01L27/11582 ,  H01L29/10 ,  H01L23/528 ,  H01L29/786 ,  H01L27/11573 ,  H01L27/1157 ,  G11C16/30 ,  G11C16/14 ,  G11C16/26 ,  H01L23/532 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/04 ,  H01L29/06

摘要： A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

公开(公告)号：US20190319044A1

公开(公告)日：2019-10-17

申请号：US16447406

申请日：2019-06-20

申请人： SUNRISE MEMORY CORPORATION

发明人： Eli Harari

IPC分类号： H01L27/11582 ,  H01L29/10 ,  G11C16/04 ,  H01L27/11565 ,  H01L23/532 ,  H01L23/522 ,  G11C16/26 ,  G11C16/14 ,  G11C16/30 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/786 ,  H01L23/528 ,  H01L29/06

摘要： A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

公开(公告)号：US10381378B1

公开(公告)日：2019-08-13

申请号：US16252301

申请日：2019-01-18

申请人： SUNRISE MEMORY CORPORATION

发明人： Eli Harari

IPC分类号： G11C11/00 ,  H01L27/11582 ,  G11C16/26 ,  H01L23/528 ,  H01L29/786 ,  H01L27/11573 ,  H01L27/1157 ,  G11C16/30 ,  G11C16/14 ,  H01L29/06 ,  H01L23/532 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/04 ,  H01L29/10

摘要： A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

公开(公告)号：US20190156900A1

公开(公告)日：2019-05-23

申请号：US16193292

申请日：2018-11-16

申请人： Sunrise Memory Corporation

发明人： Raul Adrian Cernea

IPC分类号： G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C16/32 ,  H01L27/11582 ,  G11C16/04

摘要： Algorithms for fast data retrieval, low power consumption in a 3D or planar non-volatile array of memory cells, connected between an accessible drain string and a floating, not directly accessible, source string, in a NOR-logic type of architecture, are presented.

公开(公告)号：US20180366485A1

公开(公告)日：2018-12-20

申请号：US16006612

申请日：2018-06-12

申请人： Sunrise Memory Corporation

发明人： Eli Harari ,  Raul Adrian Cernea

IPC分类号： H01L27/11578 ,  G11C7/18 ,  G11C16/04 ,  H03K19/20 ,  H03K19/177

摘要： A NOR string includes a number of individually addressable thin-film storage transistors sharing a bit line, with the individually addressable thin-film transistors further grouped into a predetermined number of segments. In each segment, the thin-film storage transistors of the segment share a source line segment, which is electrically isolated from other source line segments in the other segments within the NOR string. The NOR string may be formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, with each active strip including first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the shared bit line and each source line segment are formed in the first and second semiconductor sublayers, respectively.

公开(公告)号：US09911497B1

公开(公告)日：2018-03-06

申请号：US15783201

申请日：2017-10-13

申请人： SUNRISE MEMORY CORPORATION

发明人： Eli Harari

IPC分类号： G11C16/04 ,  G11C11/56 ,  H01L29/786 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L29/16 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/04 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/06 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/02 ,  G11C16/34 ,  G11C16/28 ,  G11C16/26 ,  G11C16/10 ,  H01L29/792

CPC分类号： G11C16/0466 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3427 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28282 ,  H01L21/32133 ,  H01L21/76892 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6675 ,  H01L29/66833 ,  H01L29/78642 ,  H01L29/7926

摘要： A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings.

公开(公告)号：US12096630B2

公开(公告)日：2024-09-17

申请号：US16577469

申请日：2019-09-20

申请人： SUNRISE MEMORY CORPORATION

发明人： Raul Adrian Cernea ,  Wu-Yi Henry Chien ,  Eli Harari

IPC分类号： H10B43/20 ,  H01L21/285 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B43/30

CPC分类号： H10B43/20 ,  H01L21/28525 ,  H01L21/30604 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53271 ,  H10B43/30

摘要： Various methods and various staircase structures formed out of the active strips of a memory structure (e.g., a memory array having a three-dimensional arrangement of NOR memory strings) above a semiconductor substrate allows efficient electrical connections to semiconductor layers within the active strips.

公开(公告)号：US12073082B2

公开(公告)日：2024-08-27

申请号：US18306073

申请日：2023-04-24

申请人： SUNRISE MEMORY CORPORATION

发明人： Youn Cheul Kim ,  Richard S. Chernicoff ,  Khandker Nazrul Quader ,  Robert D. Norman ,  Tianhong Yan ,  Sayeef Salahuddin ,  Eli Harari

IPC分类号： G11C11/00 ,  G06F3/06 ,  H01L23/00 ,  H01L25/18

CPC分类号： G06F3/0611 ,  G06F3/0631 ,  H01L24/20 ,  H01L25/18 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2924/1431 ,  H01L2924/1435

摘要： A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.

公开(公告)号：US20240179919A1

公开(公告)日：2024-05-30

申请号：US18436365

申请日：2024-02-08

申请人： SunRise Memory Corporation

发明人： Tianhong Yan ,  Scott Brad Herner ,  Jie Zhou ,  Wu-Yi Henry Chien ,  Eli Harari

IPC分类号： H10B43/40 ,  H01L21/02 ,  H01L21/225 ,  H01L21/311 ,  H01L21/3205 ,  H01L23/528 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H10B43/10 ,  H10B43/27

CPC分类号： H10B43/40 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/2251 ,  H01L21/31111 ,  H01L21/32053 ,  H01L23/528 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66742 ,  H01L29/78642 ,  H10B43/10 ,  H10B43/27

摘要： A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

公开(公告)号：US20240161837A1

公开(公告)日：2024-05-16

申请号：US18420073

申请日：2024-01-23

申请人： SUNRISE MEMORY CORPORATION

发明人： Eli Harari

IPC分类号： G11C16/34 ,  G06F17/16 ,  G06N3/063 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  H01L21/28 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/786 ,  H01L29/792 ,  H01L29/92 ,  H10B43/27

CPC分类号： G11C16/3431 ,  G06F17/16 ,  G06N3/063 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/78633 ,  H01L29/7926 ,  H01L29/92 ,  H10B43/27 ,  H10B43/10

摘要： A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.