公开(公告)号：US5578841A

公开(公告)日：1996-11-26

申请号：US573979

申请日：1995-12-18

申请人： Barbara Vasquez ,  Irenee M. Pages ,  E. James Prendergast

发明人： Barbara Vasquez ,  Irenee M. Pages ,  E. James Prendergast

IPC分类号： H01L21/336 ,  H01L23/13 ,  H01L29/417 ,  H01L29/78 ,  H01L27/148 ,  H01L29/768 ,  H01L29/80 ,  H01L23/48

CPC分类号： H01L29/66712 ,  H01L23/13 ,  H01L29/7802 ,  H01L29/41741 ,  H01L2924/0002 ,  H01L2924/13091

摘要： A multiple output, vertical MOSFET device (11) with improved electrical performance and thermal dissipation is integrated with an additional semiconductor device or semiconductor circuit (18) on a single semiconductor substrate (34). The method of making the vertical MOSFET device (11) involves thinning the semiconductor substrate (34) after fabricating the vertical MOSFET device (11) and the semiconductor circuit (18) to reduce the vertical component of electrical and thermal resistance and to increase the thermal dissipation efficiency. Electrical performance is improved by thinning the semiconductor substrate (34) and by providing a low resistivity, patterned metal buried layer. Thermal management is enhanced by using flip chip bumps (24) to dissipate heat from a top surface (31) of the semiconductor substrate (34) and by using the patterned buried metal layer (26) to dissipate heat from a bottom surface (32) of the semiconductor substrate (34).

摘要翻译： 具有改善的电性能和散热的多输出垂直MOSFET器件（11）与单个半导体衬底（34）上的附加半导体器件或半导体电路（18）集成。 制造垂直MOSFET器件（11）的方法涉及在制造垂直MOSFET器件（11）和半导体电路（18）之后使半导体衬底（34）变薄以减小电阻和热阻的垂直分量并增加热 耗散效率。 通过使半导体衬底（34）变薄并且通过提供低电阻率图案化的金属掩埋层来改善电性能。 通过使用倒装芯片凸块（24）来从半导体衬底（34）的顶表面（31）散发热量并且通过使用图案化的掩埋金属层（26）来散热来自底表面（32）的热来增强散热管理， 的半导体衬底（34）。

公开(公告)号：US5556808A

公开(公告)日：1996-09-17

申请号：US268986

申请日：1994-06-30

申请人： William M. Williams ,  Barbara Vasquez ,  Marlene J. Begay ,  Patrick Thompson

发明人： William M. Williams ,  Barbara Vasquez ,  Marlene J. Begay ,  Patrick Thompson

IPC分类号： H01L21/58 ,  H01L29/06 ,  H01L21/60

CPC分类号： H01L24/83 ,  H01L24/32 ,  H01L29/0657 ,  H01L2224/32057 ,  H01L2224/83136 ,  H01L2224/8319 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/07802 ,  H01L2924/10158 ,  Y10S438/975

摘要： A system and method for aligning a semiconductor device (10) to a fixture (11) is provided. A first physical alignment feature (12) on the semiconductor device (10) and a second physical alignment (24) on the fixture (11) mate to align and hold the semiconductor device (10) in place. In one embodiment the physical alignment features (12) and (24) are produced using standard photolithography techniques, resulting in precise alignment features. In another embodiment the physical alignment features (12) and (24) are designed and placed to control the direction the thermal expansion of the semiconductor device (10) relative to the fixture (11).

摘要翻译： 提供了一种用于将半导体器件（10）对准固定器（11）的系统和方法。 半导体器件（10）上的第一物理对准特征（12）和固定装置（11）上的第二物理对准（24）配合以将半导体器件（10）对准和保持就位。 在一个实施例中，使用标准光刻技术产生物理对准特征（12）和（24），导致精确对准特征。 在另一个实施例中，物理对准特征（12）和（24）被设计和放置以控制半导体器件（10）相对于固定装置（11）的热膨胀的方向。

公开(公告)号：US5084407A

公开(公告)日：1992-01-28

申请号：US709928

申请日：1991-06-03

申请人： Bernard W. Boland ,  Barbara Vasquez ,  James Jen-Ho Wang

发明人： Bernard W. Boland ,  Barbara Vasquez ,  James Jen-Ho Wang

IPC分类号： H01L21/76 ,  H01L21/20 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/762

CPC分类号： H01L21/02024 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/31053 ,  H01L21/76294 ,  Y10S438/969 ,  Y10S438/977

摘要： A method is described for planarizing isolated regions (12) and active regions (22) of a semiconductor wafer (10). Semiconductor wafer (10) is provided with islands of dielectric (12) that cover portions of the semiconductor wafer (10), while leaving other portions of the semiconductor wafer (10) exposed. The dielectric islands (12) have a polysilicon layer (13) that covers the dielectric islands' (12) top surface. A blanket layer of silicon is deposited on the polysilicon layer (13) that covers the top surface of the dielectric islands and is deposited between the dielectric islands (12). Planarizing the blanket layer of epitaxial silicon is achieved by a chemical-mechanical means, thereby producing a planar surface of isolated areas (12) and active areas (22).

摘要翻译： 描述了用于平坦化半导体晶片（10）的隔离区域（12）和有源区域（22）的方法。 半导体晶片（10）设置有覆盖半导体晶片（10）的部分的绝缘体岛，同时使半导体晶片（10）的其它部分露出。 电介质岛（12）具有覆盖介电岛（12）顶表面的多晶硅层（13）。 在覆盖电介质岛的顶表面的多晶硅层（13）上沉积硅层，并沉积在介质岛（12）之间。 通过化学机械装置实现平面化外延硅的覆盖层，由此产生隔离区域（12）和有源区域（22）的平坦表面。

公开(公告)号：US5028559A

公开(公告)日：1991-07-02

申请号：US327632

申请日：1989-03-23

申请人： Peter J. Zdebel ,  Barbara Vasquez

发明人： Peter J. Zdebel ,  Barbara Vasquez

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/033 ,  H01L21/316 ,  H01L21/32 ,  H01L21/339

CPC分类号： H01L28/20 ,  H01L21/033 ,  H01L21/32 ,  H01L29/66954

摘要： A method of fabrication of a device having laterally isolated semiconductor regions. In a preferred embodiment, laterally isolated polysilicon features are created with vertical, nitride-sealed sidewalls. The nitride-sealed sidewalls formed using sidewall spacer technology eliminate oxide encroachment while further preventing the loss of dopant laterally during thermal processing. The final structure comprises polysilicon features flanked by either oxide isolation or additional polysilicon features and is planar without requiring a planarization etchback. The process is applicable to polysilicon electrodes over active areas as well as polysilicon resistors over isolation oxide.

公开(公告)号：US07230437B2

公开(公告)日：2007-06-12

申请号：US10868425

申请日：2004-06-15

申请人： Benjamin N. Eldridge ,  Barbara Vasquez ,  Makarand S. Shinde ,  Gaetan L. Mathieu ,  A. Nicholas Sporck

发明人： Benjamin N. Eldridge ,  Barbara Vasquez ,  Makarand S. Shinde ,  Gaetan L. Mathieu ,  A. Nicholas Sporck

IPC分类号： G01R13/02

CPC分类号： G01R31/2889 ,  G01R1/0416 ,  G01R1/07307

摘要： A wafer test assembly includes multiple probe head substrates arranged like tiles with connectors attached to one side and probes supported on the opposing side. In one embodiment, flexible cable connectors directly connect the connectors on the probe head tile to a test head, while in another embodiment the flexible cables connect the probe head tile to a PCB providing horizontal routing to test head connectors. In one embodiment, leveling pins provide a simplified support structure connecting to a retaining element attached to the tiles to provide for applying a push-pull leveling force. A test head connector interface frame enables rearrangement of connectors between the test head and the probe card to provide for both full wafer contact or partial wafer contact. The test head connectors are rearranged by being slidable on rails, and unpluggable using pins, enabling movement over a range of positions.

摘要翻译： 晶片测试组件包括多个探针头基底，其布置成瓦片，其中连接器连接到一侧，探针支撑在相对侧上。 在一个实施例中，柔性电缆连接器将探头头瓦片上的连接器直接连接到测试头，而在另一实施例中，柔性电缆将探头头瓦片连接到PCB，从而为测试头连接器提供水平布线。 在一个实施例中，调平销提供连接到附接到瓦片的保持元件以提供施加推挽平整力的简化支撑结构。 测试头连接器接口框架能够重新布置测试头和探针卡之间的连接器，以提供完整的晶片接触或部分晶片接触。 测试头连接器通过在轨道上滑动来重新布置，并且使用引脚可拔出，使得能够在一定范围的位置上移动。

公开(公告)号：US07176131B2

公开(公告)日：2007-02-13

申请号：US10960994

申请日：2004-10-12

申请人： Georg Meyer-Berg ,  Barbara Vasquez

发明人： Georg Meyer-Berg ,  Barbara Vasquez

IPC分类号： H01L21/44

CPC分类号： H01L21/4853 ,  H01L21/486 ,  H01L23/142 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/3025 ,  H05K1/0306 ,  H05K3/4046 ,  H05K2201/0323 ,  H05K2201/10287 ,  H05K2203/0235 ,  H01L2924/00

摘要： An electronic component has a semiconductor chip and microscopically small flip-chip contacts belonging to a rewiring plate, on which macroscopically large elastic external contacts are arranged. The rewiring plate has a wiring support made of polycrystalline silicon, amorphous glass, or metal. Furthermore, the present invention relates to a method for the production of a suitable wiring support and of the electronic component.

摘要翻译： 电子部件具有属于重新布线板的半导体芯片和微小尺寸的倒装芯片触点，布置有宏观上大的弹性外部触点。 再布线板具有由多晶硅，非晶玻璃或金属制成的布线支撑。 此外，本发明涉及一种用于生产合适的布线支撑件和电子部件的方法。

公开(公告)号：US06521512B2

公开(公告)日：2003-02-18

申请号：US09970977

申请日：2001-10-04

申请人： Barbara Vasquez

发明人： Barbara Vasquez

IPC分类号： H01L2146

CPC分类号： H01L21/302 ,  H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2924/0002 ,  Y10S438/977 ,  H01L2924/00

摘要： In a method for fabricating a silicon-on-insulation wafer having fully processed devices in its upper-most silicon layer, the wafer is reduced in thickness from a surface opposite to the device layer surface by performing a first etching step of etching the semiconductor substrate to the insulation layer, so that the insulation layer functions as an etch stop layer, and a second etching step of etching the insulation layer to the semiconductor device layer, so that the semiconductor device layer functions as an etch stop layer. The semiconductor device layer is then separated into individual chips for fabricating a three-dimensionally integrated circuit thereof.

公开(公告)号：US5108946A

公开(公告)日：1992-04-28

申请号：US559460

申请日：1990-07-27

申请人： Peter J. Zdebel ,  Barbara Vasquez ,  Hang M. Liaw ,  Christian A. Seelbach

发明人： Peter J. Zdebel ,  Barbara Vasquez ,  Hang M. Liaw ,  Christian A. Seelbach

IPC分类号： H01L21/74 ,  H01L21/763

CPC分类号： H01L21/763 ,  H01L21/743

摘要： A method of forming planar isolation regions in semiconductor structures includes providing a semiconductor substrate and forming a semiconductor layer thereon. A dielectric layer comprising at least two different dielectric materials is disposed on the semiconductor layer and a trench is etched therethrough and into the semiconductor layer. Dielectric sidewalls are formed in the trench which is then filled by selectively forming depositing polycrystalline silicon therein. The semiconductor material is then at least partially oxidized to form the planar isolation region. The isolation regions disclosed herein may be used for both intradevice and interdevice isolation.

摘要翻译： 在半导体结构中形成平面隔离区域的方法包括提供半导体衬底并在其上形成半导体层。 包含至少两种不同介电材料的电介质层设置在半导体层上，并且通过其蚀刻沟槽并进入半导体层。 介质侧壁形成在沟槽中，然后通过选择性地在其中沉积多晶硅来填充沟槽。 然后将半导体材料至少部分地氧化以形成平面隔离区域。 本文公开的隔离区域可以用于室内和隔离隔离。

公开(公告)号：US5026663A

公开(公告)日：1991-06-25

申请号：US382879

申请日：1989-07-21

申请人： Peter J. Zdebel ,  Barbara Vasquez

发明人： Peter J. Zdebel ,  Barbara Vasquez

IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/225 ,  H01L21/28 ,  H01L21/285 ,  H01L21/331 ,  H01L21/336 ,  H01L29/732 ,  H01L29/78

CPC分类号： H01L21/2257 ,  H01L21/033 ,  H01L21/28525

摘要： A method of fabricating a semiconductor structure having self-aligned diffused junctions is provided wherein a first dielectric layer, a doped semiconductor layer and a second dielectric layer are formed on a semiconductor substrate. An opening extending to the semiconductor substrate is then formed through these layers. Undoped semiconductor spacers are formed in the opening adjacent to the exposed ends of the doped semiconductor layer and dopant is diffused from the doped semiconductor layer through the undoped semiconductor spacers and into the semiconductor substrate to form junctions therein. This provides for integrated contacts through the doped semiconductor layer.

公开(公告)号：US4994406A

公开(公告)日：1991-02-19

申请号：US431420

申请日：1989-11-03

申请人： Barbara Vasquez ,  Peter J. Zoebel

发明人： Barbara Vasquez ,  Peter J. Zoebel

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/06

CPC分类号： H01L21/76202 ,  H01L21/76264 ,  H01L21/763 ,  H01L21/76272 ,  H01L21/76281

摘要： A method of fabricating a semiconductor structure includes forming a thermal oxide layer, a polysilicon layer and a first dielectric layer on a substrate and using a mask to form at least one opening therein. Dielectric spacers are then formed in the opening and a trench having a self-aligned reduction in width due to the dielectric spacers is etched into the substrate beneath the opening. A dielectric trench liner is then formed prior to filling the trench with polysilicon. A second mask is then used to form isolation element openings in the first dielectric layer in which shallow isolation elements are formed.