公开(公告)号：US20160163879A1

公开(公告)日：2016-06-09

申请号：US15009906

申请日：2016-01-29

申请人： GLOBALFOUNDRIES Inc.

发明人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L27/12

CPC分类号： H01L29/78648 ,  H01L21/28008 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42364

摘要： A semiconductor device is disclosed. The semiconductor device can include a first dielectric layer disposed on a substrate; a set of bias lines disposed on the first dielectric layer; a second dielectric layer disposed on the first dielectric layer and between the set of bias lines, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer; a patterned semiconductor layer disposed on portions of the second dielectric layer; and a set of devices disposed on the patterned semiconductor layer above the set of bias lines.

摘要翻译： 公开了一种半导体器件。 半导体器件可以包括设置在衬底上的第一介电层; 设置在所述第一电介质层上的一组偏置线; 第二电介质层，设置在所述第一电介质层上和所述一组偏置线之间，其中所述第二电介质层的厚度小于所述第一介电层的厚度; 设置在所述第二电介质层的部分上的图案化半导体层; 以及设置在所述偏置线组之上的图案化半导体层上的一组器件。

公开(公告)号：US09349835B2

公开(公告)日：2016-05-24

申请号：US14027720

申请日：2013-09-16

申请人： GLOBALFOUNDRIES Inc.

发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Charan Veera Venkata Satya Surisetty

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L29/49 ,  H01L29/417 ,  H01L29/51

CPC分类号： H01L27/0886 ,  H01L21/76837 ,  H01L21/76897 ,  H01L21/823468 ,  H01L29/41766 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

摘要： A semiconductor device includes gates and a low-k spacer. The low-k spacer includes low-k spacer portions formed upon the gate sidewalls and a low-k spacer portion formed upon a top surface of an underlying substrate adjacent to the gates. When a structure has previously undergone a gate processing fabrication stage, the gates and at least a portion of the top surface of the substrate may be exposed thereby allowing the formation of the low-k spacer. This exposure may include removing any original gate spacers, removing an original liner formed upon the original spacers, and removing any original fill material formed upon the liner.

摘要翻译： 半导体器件包括栅极和低k间隔物。 低k间隔物包括形成在栅极侧壁上的低k隔离部分和形成在与栅极相邻的下面基底的顶表面上的低k隔离部分。 当结构先前已经进行了栅极处理制造阶段时，可以暴露栅极和衬底顶表面的至少一部分，从而允许形成低k间隔物。 该曝光可以包括去除任何原始的栅极间隔物，去除形成在原始间隔物上的原始衬垫，以及去除在衬垫上形成的任何原始填充材料。

公开(公告)号：US09349658B1

公开(公告)日：2016-05-24

申请号：US14608625

申请日：2015-01-29

申请人： GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

发明人： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim

IPC分类号： H01L29/66 ,  H01L21/84 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311

CPC分类号： H01L21/845 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

摘要： One illustrative embodiment involves forming a plurality of trenches in a substrate so as to define a fin, forming a first oxidation-blocking layer of insulating material in the trenches so as to cover a portion, but not all, of the sidewalls of the lower portion of the fin, forming a second layer of insulating material above the first oxidation-blocking layer of insulating material, and performing a thermal anneal process to convert part, but not all, of the lower portion of the fin positioned above the first oxidation-blocking layer of insulating material into an oxide fin isolation region positioned under the fin.

摘要翻译： 一个说明性实施例涉及在衬底中形成多个沟槽以限定翅片，在沟槽中形成绝缘材料的第一氧化阻挡层，以便覆盖下部分的侧壁的一部分但不是全部 在绝缘材料的第一氧化阻挡层之上形成第二绝缘材料层，并进行热退火处理以将位于第一氧化阻挡层之上的翅片的下部的部分转化而不是全部 绝缘材料层形成位于翅片下方的氧化物鳍片隔离区域。

公开(公告)号：US09343320B2

公开(公告)日：2016-05-17

申请号：US14098650

申请日：2013-12-06

申请人： GLOBALFOUNDRIES INC.

发明人： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

IPC分类号： H01L27/108 ,  H01L21/306 ,  H01L21/308 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/84 ,  H01L29/66 ,  H01L29/94 ,  H01L27/12

CPC分类号： H01L21/30604 ,  H01L21/3081 ,  H01L21/84 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

摘要： Dummy deep trenches can be formed within a logic device region in which logic devices are to be formed while deep trench capacitors are formed within a memory device region. Semiconductor fins are formed over a top surface prior to forming trenches, and disposable material is filled around said semiconductor fins. A top surface of said disposable filler material layer can be coplanar with a top surface of said semiconductor fins, which eases deep trench formation. Conductive material portions of the dummy deep trenches can be recessed to avoid electrical contact with semiconductor fins within the logic device region, while an inner electrode of each deep trench can contact a semiconductor fin within the memory device region. A dielectric material portion can be formed above each conductive material portion of a dummy deep trench.

摘要翻译： 虚拟深沟槽可以形成在其中将在存储器件区域内形成深沟槽电容器的逻辑器件区域内形成逻辑器件。 半导体翅片在形成沟槽之前形成在顶表面上，并且一次性材料填充在所述半导体鳍片周围。 所述一次性填充材料层的顶表面可以与所述半导体鳍片的顶表面共面，这使得深沟槽形成更容易。 虚拟深沟槽的导电材料部分可以凹入以避免与逻辑器件区域内的半导体鳍片的电接触，而每个深沟槽的内部电极可接触存储器件区域内的半导体鳍片。 可以在虚拟深沟槽的每个导电材料部分上方形成电介质材料部分。

公开(公告)号：US09337315B2

公开(公告)日：2016-05-10

申请号：US14157851

申请日：2014-01-17

申请人： GLOBALFOUNDRIES INC.

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L21/265 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/26586 ,  H01L21/823431 ,  H01L29/66803 ,  H01L29/785

摘要： A FinFET having spacers with a substantially uniform profile along the length of a gate stack which covers a portion of a fin of semiconductor material formed on a substrate is provided by depositing spacer material conformally on both the fins and gate stack and performing an angled ion impurity implant approximately parallel to the gate stack to selectively cause damage to only spacer material deposited on the fin. Due to the damage caused by the angled implant, the spacer material on the fins can be etched with high selectivity to the spacer material on the gate stack.

公开(公告)号：US09337259B2

公开(公告)日：2016-05-10

申请号：US14154438

申请日：2014-01-14

申请人： GLOBALFOUNDRIES INC.

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Pranita Kerber ,  Ali Khakifirooz ,  Balasubramanian Pranatharthiharan

IPC分类号： H01L29/06 ,  H01L21/84 ,  H01L21/762 ,  H01L29/66

CPC分类号： H01L29/0653 ,  H01L21/76224 ,  H01L21/84 ,  H01L29/66545

摘要： A structure to improve ETSOI MOSFET devices includes a wafer having regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in the hole.

摘要翻译： 改进ETSOI MOSFET器件的结构包括具有至少覆盖在第二半导体层上的氧化物层上的第一半导体层的区域的晶片。 这些区域由至少部分地延伸到第二半导体层中并且部分地填充有电介质的STI分开。 栅极结构形成在第一半导体层之上，并且在涉及的湿清洗期间，STI纹理腐蚀直到其处于低于氧化物层的水平。 在器件上沉积另一个介电层，并蚀刻一个孔以到达源极和漏极区。 孔没有完全着陆，至少部分地延伸到STI中，并且绝缘材料沉积在孔中。

公开(公告)号：US09330908B2

公开(公告)日：2016-05-03

申请号：US13925911

申请日：2013-06-25

申请人： GLOBALFOUNDRIES INC.

发明人： Thomas N. Adam ,  Kangguo Cheng ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC分类号： H01L21/02 ,  H01L21/8258 ,  H01L21/8238 ,  H01L27/088

CPC分类号： H01L21/02538 ,  H01L21/02373 ,  H01L21/02441 ,  H01L21/02447 ,  H01L21/02494 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/088

摘要： A semiconductor structure includes a first semiconductor region. The first semiconductor region includes a first semiconductor layer composed of a group IV semiconductor material having a top surface and a back surface. The first semiconductor layer has an opening in the top surface to at least a depth greater than an aspect ratio trapping (ART) distance. The first semiconductor region also has a second semiconductor layer composed of a group III/V semiconductor compound deposited within the opening and on the top surface of the first semiconductor layer. The second semiconductor layer forms an ART region from the bottom of the opening to the ART distance.

摘要翻译： 半导体结构包括第一半导体区域。 第一半导体区域包括由具有顶表面和后表面的IV族半导体材料组成的第一半导体层。 第一半导体层在顶表面具有至少大于纵横比捕获（ART）距离的深度的开口。 第一半导体区域还具有由沉积在第一半导体层的开口内和顶表面上的III / V族半导体化合物构成的第二半导体层。 第二半导体层从开口的底部到ART距离形成ART区域。

公开(公告)号：US09324797B2

公开(公告)日：2016-04-26

申请号：US14751761

申请日：2015-06-26

申请人： GLOBALFOUNDRIES INC.

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC分类号： H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L51/00 ,  H01L29/49 ,  H01L29/775 ,  H01L29/423 ,  H01L29/51 ,  H01L29/10 ,  H01L29/786 ,  H01L29/08

CPC分类号： H01L29/42392 ,  H01L21/8238 ,  H01L21/82385 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78696 ,  H01L51/0048

摘要： A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.

公开(公告)号：US09287130B1

公开(公告)日：2016-03-15

申请号：US14676345

申请日：2015-04-01

申请人： GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation ,  STMicroelectronics, Inc.

发明人： Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Ruilong Xie ,  Bruce Doris ,  Kangguo Cheng ,  Jason R. Cantone ,  Sylvie Mignot ,  David Moreau ,  Muthumanickam Sankarapandian ,  Pierre Morin ,  Su Chen Fan ,  Kisik Choi ,  Murat K. Akarvardar

IPC分类号： H01L21/00 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266

CPC分类号： H01L21/823431 ,  H01L21/30604 ,  H01L21/845 ,  H01L29/66795

摘要： A method includes forming a plurality of fin elements above a substrate. A mask is formed above the substrate. The mask has an opening defined above at least one selected fin element of the plurality of fin elements. An ion species is implanted into the at least one selected fin element through the opening to increase its etch characteristics relative to the other fin elements. The at least one selected fin element is removed selectively relative to the other fin elements.

摘要翻译： 一种方法包括在基底上形成多个翅片元件。 在基板上形成掩模。 掩模具有限定在多个翅片元件中的至少一个选定翅片元件上方的开口。 通过开口将离子物质注入到至少一个选定的翅片元件中，以相对于其它翅片元件增加其蚀刻特性。 选择性地将至少一个选定的翅片元件相对于其它翅片元件移除。

公开(公告)号：US09281198B2

公开(公告)日：2016-03-08

申请号：US13900808

申请日：2013-05-23

申请人： GLOBALFOUNDRIES INC.

发明人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

IPC分类号： H01L21/28 ,  H01L21/84 ,  H01L29/786 ,  H01L27/12

CPC分类号： H01L29/78648 ,  H01L21/28008 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42364

摘要： A method of forming a semiconductor device is disclosed. The method includes forming a first dielectric layer on a substrate; forming a set of bias lines on the first dielectric layer; covering the set of bias lines with a second dielectric layer; forming a semiconductor layer on the second dielectric layer; and forming a set of devices on the semiconductor layer above the set of bias lines.

摘要翻译： 公开了一种形成半导体器件的方法。 该方法包括在基底上形成第一介电层; 在所述第一电介质层上形成一组偏置线; 用第二电介质层覆盖该组偏置线; 在所述第二电介质层上形成半导体层; 以及在所述偏置线组之上的半导体层上形成一组器件。