公开(公告)号：US10068902B1

公开(公告)日：2018-09-04

申请号：US15715220

申请日：2017-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Hsien-Ching Lo ,  Yongjun Shi ,  Randy W. Mann ,  Yi Qi ,  Guowei Xu ,  Wei Hong ,  Jerome Ciavatti ,  Jae Gon Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/06 ,  H01L29/66

Abstract: Disclosed is a method of forming an integrated circuit (IC) structure with multiple non-planar transistors having different effective channel widths. In the method, sacrificial gates are removed from partially completed transistors, creating gate openings that expose sections of semiconductor fins between source/drain regions. Prior to forming replacement metal gates in the gate openings, additional process steps are performed so that, in the resulting IC structure, some transistors have different channel region heights and, thereby different effective channel widths, than others. These steps can include forming isolation regions in the bottoms of some gate openings. Additionally or alternatively, these steps can include filling some gate openings with a sacrificial material, recessing the sacrificial material to expose fin tops within those gate openings, either recessing the fin tops or forming isolation regions in the fin tops, and removing the sacrificial material. Also disclosed is an IC structure formed according to the method.

公开(公告)号：US20180047641A1

公开(公告)日：2018-02-15

申请号：US15792357

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vara G. Reddy Vakada ,  Laegu Kang ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Srikanth Balaji Samavedam ,  Sri Charan Vemula ,  Manfred Eller

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0928

Abstract: A device includes a substrate having an N-active region and a P-active region, a layer of silicon-carbon positioned on an upper surface of the N-active region, a first layer of a first semiconductor material positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on an upper surface of the P-active region, and a layer of a second semiconductor material positioned on the second layer of the first semiconductor material. An N-type transistor is positioned in and above the N-active region and a P-type transistor is positioned in and above the P-active region.

公开(公告)号：US09431539B2

公开(公告)日：2016-08-30

申请号：US14511715

申请日：2014-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Catherine B. Labelle ,  Xiuyu Cai

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/78 ,  H01L27/12 ,  H01L29/10 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/7849 ,  B82Y10/00 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66818 ,  H01L29/775

Abstract: A dual-strained Si and SiGe FinFET device with dielectric isolation and a dual-strained nanowire device and methods of forming them are provided. Embodiments include a SiGe SRB formed on a silicon substrate, the SRB having a first region and a second region; a first and a second dielectric isolation layer formed on the first region and on the second region of the SiGe SRB, respectively; a tensile strained Si fin formed on the first dielectric isolation layer; a compressive strained SiGe fin formed on the second dielectric isolation layer; first source/drain regions formed at opposite sides of the tensile strained Si fin; second source/drain regions formed at opposite sides of the compressive strained SiGe fin; a first RMG formed between the first source/drain regions; and a second RMG formed between the second source/drain regions.

Abstract translation: 提供具有绝缘隔离的双应变Si和SiGe FinFET器件和双应变纳米线器件及其形成方法。 实施例包括形成在硅衬底上的SiGe SRB，SRB具有第一区域和第二区域; 分别形成在SiGe SRB的第一区域和第二区域上的第一和第二介电隔离层; 形成在第一介电隔离层上的拉伸应变Si翅片; 形成在所述第二介电隔离层上的压缩应变SiGe鳍; 形成在拉伸应变Si翅片的相对侧的第一源极/漏极区域; 形成在压缩应变SiGe翅片的相对侧的第二源极/漏极区域; 形成在第一源/漏区之间的第一RMG; 以及形成在第二源/漏区之间的第二RMG。

公开(公告)号：US09391140B2

公开(公告)日：2016-07-12

申请号：US14309956

申请日：2014-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Xunyuan Zhang ,  Catherine B. Labelle

IPC: H01L21/8242 ,  H01L29/06 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/02532 ,  H01L21/02639 ,  H01L21/311 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of fabricating raised fin structures is provided, the fabricating including: providing a substrate and at least one dielectric layer over the substrate; forming a trench in the at least one dielectric layer, the trench having a lower portion, a lateral portion, and an upper portion, the upper portion being at least partially laterally offset from the lower portion and being joined to the lower portion by the lateral portion; and, growing a material in the trench to form the raised fin structure, wherein the trench is formed to ensure that any growth defect in the lower portion of the trench terminates either in the lower portion or the lateral portion of the trench and does not extend into the upper portion of the trench.

Abstract translation: 提供一种制造凸起翅片结构的方法，所述制造方法包括：在衬底上提供衬底和至少一个电介质层; 在所述至少一个电介质层中形成沟槽，所述沟槽具有下部，侧部和上部，所述上部至少部分地从所述下部向外偏移并且通过所述侧部与所述下部 一部分; 并且在沟槽中生长材料以形成凸起的翅片结构，其中形成沟槽以确保沟槽的下部中的任何生长缺陷终止于沟槽的下部或横向部分，并且不延伸 进入沟槽的上部。

公开(公告)号：US20150318169A1

公开(公告)日：2015-11-05

申请号：US14267634

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar ,  David Paul Brunco

IPC: H01L21/02 ,  H01L29/161 ,  H01L29/66

CPC classification number: H01L29/161 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate and performing an epitaxial deposition process using a combination of silane (SiH4), dichlorosilane (SiH2Cl2), germane (GeH4) and a carrier gas to form an epi semiconductor material around the fin, wherein the flow rate of dichlorosilane used during the epitaxial deposition process is equal to 10-90% of the combined flow rate of silane and dichlorosilane.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底中形成翅片并使用硅烷（SiH 4），二氯硅烷（SiH 2 Cl 2），锗烷（GeH 4）和载气的组合进行外延沉积工艺以形成外延 散热片周围的半导体材料，其中在外延沉积工艺期间使用的二氯硅烷的流速等于硅烷和二氯硅烷的组合流速的10-90％。

公开(公告)号：US20140159052A1

公开(公告)日：2014-06-12

申请号：US13710639

申请日：2012-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinping Liu ,  Yi Qi ,  Xiaodong Yang

IPC: H01L29/78 ,  H01L21/02

CPC classification number: H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: Embodiments of the invention provide an improved method and structure for a transistor with reduced DIBL and RON. A sigma cavity is formed in a semiconductor substrate adjacent to a transistor. The sigma cavity is filled with an epitaxially grown semiconductor material that also serves as a stress-inducing region for the purposes of increasing carrier mobility. The epitaxially grown semiconductor material is doped with a reverse doping profile. A lightly doped region lines the interior of the sigma cavity, followed by an undoped region, followed by a heavily doped region. The shape of the lightly doped region is such that it is thicker adjacent to the channel, which reduces RON, and thinner below the channel, which reduces DIBL.

Abstract translation: 本发明的实施例提供了具有减少的DIBL和RON的晶体管的改进的方法和结构。 在与晶体管相邻的半导体衬底中形成Σ腔。 填充有外延生长的半导体材料，其也用作应力诱导区域，以增加载流子迁移率。 外延生长的半导体材料掺杂有反向掺杂分布。 轻掺杂区域将西格玛腔体的内部引导，随后是未掺杂的区域，随后是重掺杂区域。 轻掺杂区域的形状使其在沟道附近较厚，这降低了RON，并且在沟道以下更薄，这降低了DIBL。

公开(公告)号：US10756184B2

公开(公告)日：2020-08-25

申请号：US16180486

申请日：2018-11-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： George R. Mulfinger ,  Timothy J. McArdle ,  Judson R. Holt ,  Steffen A. Sichler ,  Ömür I. Aydin ,  Wei Hong ,  Yi Qi ,  Hui Zang ,  Liu Jiang

IPC: H01L29/08 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L21/28

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to faceted epitaxial source/drain regions and methods of manufacture. The structure includes: a gate structure over a substrate; an L-shaped sidewall spacer located on sidewalls of the gate structure and extending over the substrate adjacent to the gate structure; and faceted diffusion regions on the substrate, adjacent to the L-shaped sidewall spacer.

公开(公告)号：US20200044029A1

公开(公告)日：2020-02-06

申请号：US16052140

申请日：2018-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. Mulfinger ,  Timothy J. McArdle ,  Jody Fronheiser ,  El Mehdi Bazizi ,  Yi Qi

IPC: H01L29/10 ,  H01L29/08 ,  H01L27/12 ,  H01L29/165 ,  H01L21/84 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/306

Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A channel region is arranged laterally between a first source/drain region and a second source/drain region. The channel region includes a first semiconductor layer and a second semiconductor layer arranged over the first semiconductor layer. A gate structure is arranged over the second semiconductor layer of the channel region The first semiconductor layer is composed of a first semiconductor material having a first carrier mobility. The second semiconductor layer is composed of a second semiconductor material having a second carrier mobility that is greater than the first carrier mobility of the first semiconductor layer.

公开(公告)号：US10546775B1

公开(公告)日：2020-01-28

申请号：US16052085

申请日：2018-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  Liu Jiang ,  Yongjun Shi ,  Yi Qi ,  Hsien-Ching Lo ,  Hui Zang

IPC: H01L21/70 ,  H01L21/768 ,  H01L27/12 ,  H01L29/66 ,  H01L21/28 ,  H01L21/84 ,  H01L21/762 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first dielectric layer is deposited over a first gate structure in a first device area and a second gate structure in a second device area, and then planarized. A second dielectric layer is deposited over the planarized first dielectric layer, and then removed from the first device area. After removing the second dielectric layer from the first device area, the first dielectric layer in the first device area is recessed to expose the first gate structure. A silicide is formed on the exposed first gate structure.

公开(公告)号：US20190341448A1

公开(公告)日：2019-11-07

申请号：US15968968

申请日：2018-05-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Emilie M.S. Bourjot ,  Julien Frougier ,  Yi Qi ,  Ruilong Xie ,  Hui Zang ,  Hsien-Ching Lo ,  Zhenyu Hu

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L29/08

Abstract: Various aspects of the disclosure include nanosheet-FET structures having a wrap-all-around contact where the contact wraps entirely around the S/D epitaxy structure, not just on the top and sides of the S/D epitaxy structure, thereby increasing contact area and ultimately allowing for improved S/D contact resistance. Other aspects of the disclosure include nanosheet-FET structures having a bottom isolation to reduce parasitic S/D leakage to the substrate.