公开(公告)号：US20160276350A1

公开(公告)日：2016-09-22

申请号：US14662734

申请日：2015-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01L27/11 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/092 ,  H01L27/0924

Abstract: A semiconductor structure includes a semiconductor substrate, at least one first elongated region of n-type or p-type, and at least one other second elongated region of the other of n-type or p-type, the first and second elongated regions crossing such that the first elongated region and the second elongated region intersect at a common area, and a shared gate structure over each common area.

Abstract translation: 半导体结构包括半导体衬底，n型或p型的至少一个第一细长区域和n型或p型另一个的至少一个另外的第二细长区域，第一和第二细长区域跨越 使得第一细长区域和第二细长区域在公共区域相交，并且在每个公共区域上共享门结构。

公开(公告)号：US20160211375A1

公开(公告)日：2016-07-21

申请号：US15082103

申请日：2016-03-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa CHI ,  Ajey JACOB ,  Abhijeet PAUL

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L27/092 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

公开(公告)号：US20160190014A1

公开(公告)日：2016-06-30

申请号：US14730614

申请日：2015-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. PATIL ,  Min-hwa CHI

IPC: H01L21/8234 ,  H01L21/324 ,  H01L21/225 ,  H01L21/283

CPC classification number: H01L21/823443 ,  H01L21/2253 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/283 ,  H01L21/285 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76889 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823835 ,  H01L21/823842

Abstract: Methods are provided for fabricating multi-layer semiconductor structures. The methods include, for example: providing a first layer and a second layer over a substrate, the first layer including a first metal and the second layer including a second metal, where the second layer is disposed over the first layer and the first metal and second metal are different metals; and annealing the first layer, the second layer, and the substrate to react at least a portion of the first metal of the first layer to form a first reacted layer and at least a portion of the second metal of the second layer to form a second reacted layer, where at least one of the first reacted layer or the second reacted layer includes at least one of a first metal silicide of the first metal or a second metal silicide of the second metal.

Abstract translation: 提供了制造多层半导体结构的方法。 所述方法包括例如：在衬底上提供第一层和第二层，第一层包括第一金属，第二层包括第二金属，其中第二层设置在第一层和第一金属之上， 第二种金属是不同的金属; 以及退火所述第一层，所述第二层和所述衬底以使所述第一层的所述第一金属的至少一部分反应以形成第一反应层和所述第二层的所述第二金属的至少一部分，以形成第二层 其中第一反应层或第二反应层中的至少一个包含第一金属的第一金属硅化物或第二金属的第二金属硅化物中的至少一种。

公开(公告)号：US20160126316A1

公开(公告)日：2016-05-05

申请号：US14526831

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Jin Ping LIU ,  Min-hwa CHI

IPC: H01L29/165 ,  H01L29/737 ,  H01L21/324 ,  H01L29/66 ,  H01L29/167 ,  H01L21/02 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/165 ,  H01L21/26506 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/66636 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7848

Abstract: Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.

Abstract translation: 提供晶体管结构和制造晶体管结构的方法。 所述方法包括：至少部分地在衬底内制造晶体管结构，所述制造包括：在所述衬底内提供空腔; 以及至少部分地在所述空腔内形成所述晶体管结构的第一部分和第二部分，所述第一部分至少部分地设置在所述基板和所述第二部分之间，其中所述第一部分禁止材料从所述第二部分扩散到所述第二部分 基质。 在一个实施例中，晶体管结构是场效应晶体管结构，并且第一部分和第二部分包括场效应晶体管结构的源极区或漏极区之一。 在另一实施例中，晶体管结构是双极结型晶体管结构。

公开(公告)号：US20150311120A1

公开(公告)日：2015-10-29

申请号：US14262882

申请日：2014-04-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shashidhar Shreeshail SHINTRI ,  Min-hwa CHI

IPC: H01L21/8234 ,  H01L21/324 ,  H01L21/02 ,  H01L29/78 ,  H01L29/267

CPC classification number: H01L21/823418 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: Methods of fabricating field effect transistors having a source region and a drain region separated by a channel region are provided which include: using a single mask step in forming a first portion(s) and a second portion(s) of at least one of the source region or the drain region, the first portion(s) including a first material selected and configured to facilitate the first portion(s) stressing the channel region, and the second portion(s) including a second material selected and configured to facilitate the second portion(s) having a lower electrical resistance than the first portion(s). One embodiment includes: providing the first material with a crystal lattice structure; and forming the second material by disposing another material interstitially with respect to the crystal lattice structure. Another embodiment includes forming the first portion and the second portion within at least one of a source cavity or a drain cavity of the semiconductor substrate.

Abstract translation: 提供了制造具有由沟道区域分隔的源极区域和漏极区域的场效应晶体管的方法，其包括：使用单个掩模步骤来形成第一部分和第二部分中的至少一个 源极区域或漏极区域，第一部分包括被选择并且被配置为便于使第一部分对通道区域施加压力的第一材料，并且第二部分包括选择和构造成促进 第二部分具有比第一部分更低的电阻。 一个实施例包括：为第一材料提供晶格结构; 以及通过相对于所述晶格结构间歇地设置另一材料来形成所述第二材料。 另一实施例包括在半导体衬底的源腔或漏腔中的至少一个中形成第一部分和第二部分。

公开(公告)号：US20150255277A1

公开(公告)日：2015-09-10

申请号：US14200197

申请日：2014-03-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wei Hua TONG ,  Tien-Ying LUO ,  Yan Ping SHEN ,  Feng ZHOU ,  Jun LIAN ,  Haoran SHI ,  Min-hwa CHI ,  Jin Ping LIU ,  Haiting WANG ,  Seung KIM

IPC: H01L21/02 ,  H01L29/51 ,  H01L21/324 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02312 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/321 ,  H01L21/324 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Abstract translation: 提供具有一个或多个氮化保形层的鳍式晶体管制造方法和结构，以提高半导体器件的可靠性。 该方法包括例如提供至少一个材料层，该材料层部分地保形地设置在衬底上延伸的翅片上，所述材料层包括栅极电介质层; 以及在所述材料层的暴露表面上进行保形氮化处理，所述共形氮化工艺形成暴露的共形氮化表面。

公开(公告)号：US20150062996A1

公开(公告)日：2015-03-05

申请号：US14017417

申请日：2013-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang LIU ,  Min-hwa CHI ,  Anurag MITTAL

IPC: H01L27/112 ,  G11C17/12 ,  H01L21/762 ,  G11C17/16 ,  H01L21/28

CPC classification number: G11C17/12 ,  G11C17/16 ,  G11C17/18 ,  H01L21/76224 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An OTP anti-fuse memory array without additional selectors and a manufacturing method are provided. Embodiments include forming wells of a first polarity in a substrate, forming a bitline of the first polarity in each well, and forming plural metal gates across each bitline, wherein no source/drain regions are formed between the metal gates.

Abstract translation: 提供了没有附加选择器的OTP反熔丝存储器阵列和制造方法。 实施例包括在衬底中形成第一极性的阱，在每个阱中形成第一极性的位线，以及在每个位线之间形成多个金属栅极，其中在金属栅极之间不形成源极/漏极区。

公开(公告)号：US20150024557A1

公开(公告)日：2015-01-22

申请号：US13943849

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang LIU ,  Min-hwa CHI

IPC: H01L29/66

CPC classification number: H01L21/26533 ,  H01L21/823878 ,  H01L29/1033 ,  H01L29/1079 ,  H01L29/4966 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/7833

Abstract: There is set forth herein a semiconductor device fabricated on a bulk wafer having a local buried oxide region underneath a channel region of a MOSFET. In one embodiment the local buried oxide region can be self-aligned to a gate, and a source/drain region can be formed in a bulk substrate. A local buried oxide region can be formed in a semiconductor device by implantation of oxygen into a bulk region of the semiconductor device followed by annealing.

Abstract translation: 这里提出了在具有在MOSFET的沟道区域下方的局部掩埋氧化物区域的体晶片上制造的半导体器件。 在一个实施例中，局部掩埋氧化物区域可以与栅极自对准，并且源极/漏极区域可以在体基板中形成。 可以在半导体器件中通过将氧注入到半导体器件的体区域中然后退火来形成局部掩埋氧化物区域。

公开(公告)号：US20180033726A1

公开(公告)日：2018-02-01

申请号：US15724563

申请日：2017-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. JACOB ,  Suraj K. PATIL ,  Min-hwa CHI

IPC: H01L23/525 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L23/5226

Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.

公开(公告)号：US20170371002A1

公开(公告)日：2017-12-28

申请号：US15190323

申请日：2016-06-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa CHI ,  Xusheng WU

IPC: G01R33/06 ,  H01L29/66 ,  H01L29/06 ,  H01L29/82 ,  H01L29/78

CPC classification number: G01R33/066 ,  G01R33/0058 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/82

Abstract: Methods for forming an efficient and effective crossed-fins FinFET device for sensing and measuring magnetic fields and resulting devices are disclosed. Embodiments include forming first-fins, parallel to and spaced from each other, in a first direction on a substrate; forming second-fins, parallel to and spaced from each other on the substrate, in a same plane as the first fins and in a second direction perpendicular to and crossing the first-fins; forming a dummy gate with a spacer on each side over channel areas of the first and second fins; forming source/drain (S/D) regions at opposite ends of each first and second fin; forming an ILD over the fins and the dummy gate and planarizing to reveal the dummy gate; removing the dummy gate, forming a cavity; and forming a high-k/metal gate in the cavity.