公开(公告)号：US20160247778A1

公开(公告)日：2016-08-25

申请号：US15144108

申请日：2016-05-02

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Arkalgud R. Sitaram

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L21/768 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/10126 ,  H01L2224/1182 ,  H01L2224/13023 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/1379 ,  H01L2224/13809 ,  H01L2224/13811 ,  H01L2224/13847 ,  H01L2224/13855 ,  H01L2224/1601 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/81007 ,  H01L2224/81048 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/8182 ,  H01L2224/81862 ,  H01L2224/81895 ,  H01L2224/81903 ,  H01L2224/81905 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01051 ,  H01L2924/01327 ,  H01L2924/364 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/2064

Abstract: An apparatus relates generally to a microelectronic device. In such an apparatus, a first substrate has a first surface with first interconnects located on the first surface, and a second substrate has a second surface spaced apart from the first surface with a gap between the first surface and the second surface. Second interconnects are located on the second surface. Lower surfaces of the first interconnects and upper surfaces of the second interconnects are coupled to one another for electrical conductivity between the first substrate and the second substrate. A conductive collar is around sidewalls of the first and second interconnects, and a dielectric layer is around the conductive collar.

Abstract translation: 一种装置一般涉及一种微电子装置。 在这样的装置中，第一基板具有第一表面，第一互连位于第一表面上，第二基板具有与第一表面间隔开的第二表面，第一表面与第二表面之间具有间隙。 第二互连位于第二表面上。 第一互连件的下表面和第二互连件的上表面彼此耦合，用于在第一基板和第二基板之间的导电性。 导电套环在第一和第二互连的侧壁周围，并且电介质层围绕导电套环。

公开(公告)号：US20160218057A1

公开(公告)日：2016-07-28

申请号：US14602984

申请日：2015-01-22

Applicant: Invensas Corporation

Inventor： Bong-Sub Lee ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Liang Wang ,  Laura Wills Mirkarimi ,  Arkalgud R. Sitaram

IPC: H01L23/498 ,  H05K3/18 ,  H05K1/16 ,  H01L21/48 ,  H05K1/11

CPC classification number: H05K1/097 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/112 ,  H05K1/113 ,  H05K1/165 ,  H05K3/188 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/5313 ,  H01L2924/00

Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130′) covered by a conductive coating (130″) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.

Abstract translation: 内插器电路（130）由可能牺牲的基板（210）形成，所述牺牲基板（210）从由导电涂层（130“）覆盖的多孔芯（130'）形成，所述导电涂层增加导电性。 核心由纳米颗粒油墨印刷。 然后形成支撑件（120S），例如 通过模制，以机械地稳定电路。 在形成电路或支撑件的同时，可以使用磁场来稳定电路。 还提供其他功能。

公开(公告)号：US20160133600A1

公开(公告)日：2016-05-12

申请号：US14980996

申请日：2015-12-28

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L21/52 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/5384 ,  H01L24/09 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/08165 ,  H01L2224/08235 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/8182 ,  H01L2224/85205 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Semiconductor integrated circuits (110) or assemblies are disposed at least partially in cavities between two interposers (120). Conductive vias (204M) pass through at least one of the interposers or at least through the interposer's substrate, and reach a semiconductor integrated circuit or an assembly. Other conductive vias (204M.1) pass at least partially through multiple interposers and are connected to conductive vias that reach, or are capacitively coupled to, a semiconductor IC or an assembly. Other features are also provided.

公开(公告)号：US09331043B1

公开(公告)日：2016-05-03

申请号：US14609720

申请日：2015-01-30

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Arkalgud R. Sitaram

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L24/81 ,  H01L21/768 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/10126 ,  H01L2224/1182 ,  H01L2224/13023 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/1379 ,  H01L2224/13809 ,  H01L2224/13811 ,  H01L2224/13847 ,  H01L2224/13855 ,  H01L2224/1601 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/81007 ,  H01L2224/81048 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/8182 ,  H01L2224/81862 ,  H01L2224/81895 ,  H01L2224/81903 ,  H01L2224/81905 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01051 ,  H01L2924/01327 ,  H01L2924/364 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/2064

Abstract: An apparatus relates generally to a microelectronic device. In such an apparatus, a first substrate has a first surface with first interconnects located on the first surface, and a second substrate has a second surface spaced apart from the first surface with a gap between the first surface and the second surface. Second interconnects are located on the second surface. Lower surfaces of the first interconnects and upper surfaces of the second interconnects are coupled to one another for electrical conductivity between the first substrate and the second substrate. A conductive collar is around sidewalls of the first and second interconnects, and a dielectric layer is around the conductive collar.

公开(公告)号：US20150357272A1

公开(公告)日：2015-12-10

申请号：US14586580

申请日：2014-12-30

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Guilian Gao

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L25/16 ,  H01L23/31

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/56 ,  H01L23/10 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/162 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/16195 ,  H01L2924/167 ,  H01L2924/16788 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83

Abstract: An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.

Abstract translation: 集成电路（IC）封装包括具有背面的第一基板和设置在其中的空腔的顶表面。 空腔具有限定前侧表面的底板。 多个第一导电触点设置在前侧表面上，并且多个第二导电触点设置在背侧表面上。 多个第一导电元件穿过第一基板并将第一和第二导电触点中的选定的彼此耦合。 包含IC的第一裸片与第一导电触点中的对应导体电连接。 第二基板具有密封地附接到第一基板的顶表面的底表面，并且介电材料设置在空腔中以封装第一模具。

公开(公告)号：US11056390B2

公开(公告)日：2021-07-06

申请号：US16718820

申请日：2019-12-18

Applicant: INVENSAS CORPORATION

Inventor： Cyprian Emeka Uzoh ,  Guilian Gao ,  Liang Wang ,  Hong Shen ,  Arkalgud R. Sitaram

IPC: H01L21/82 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/31

Abstract: A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

公开(公告)号：US10600760B2

公开(公告)日：2020-03-24

申请号：US16020654

申请日：2018-06-27

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Arkalgud R. Sitaram

IPC: H01L25/065 ,  H01L23/64 ,  H01L23/48 ,  H01L21/02 ,  H01L21/311 ,  H01L25/00 ,  H01L23/00

Abstract: Capacitive coupling of integrated circuit die components and other conductive areas is provided. Each component to be coupled has a surface that includes at least one conductive area, such as a metal pad or plate. An ultrathin layer of dielectric is formed on at least one surface to be coupled. When the two components, e.g., one from each die, are permanently contacted together, the ultrathin layer of dielectric remains between the two surfaces, forming a capacitor or capacitive interface between the conductive areas of each respective component. The ultrathin layer of dielectric may be composed of multiple layers of various dielectrics, but in one implementation, the overall thickness is less than approximately 50 nanometers. The capacitance per unit area of the capacitive interface formed depends on the particular dielectric constants κ of the dielectric materials employed in the ultrathin layer and their respective thicknesses. Electrical and grounding connections can be made at the edge of the coupled stack.

公开(公告)号：US20190198435A1

公开(公告)日：2019-06-27

申请号：US16288720

申请日：2019-02-28

Applicant: INVENSAS CORPORATION

Inventor： Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Guilian Gao

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L25/065 ,  H01L23/10 ,  H01L21/56 ,  H01L25/16 ,  H01L23/13 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/56 ,  H01L23/10 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/162 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/16195 ,  H01L2924/167 ,  H01L2924/16788 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83

Abstract: An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.

公开(公告)号：US10256177B2

公开(公告)日：2019-04-09

申请号：US15651826

申请日：2017-07-17

Applicant: INVENSAS CORPORATION

Inventor： Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Guilian Gao

IPC: H01L23/10 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L25/16 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

Abstract: An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.

公开(公告)号：US10178363B2

公开(公告)日：2019-01-08

申请号：US15280661

申请日：2016-09-29

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Guilian Gao ,  Arkalgud R. Sitaram

IPC: H04N9/04 ,  H04N9/43 ,  G02B27/10 ,  G06T1/20 ,  H01L27/146 ,  H01L31/0232 ,  H01L31/028 ,  H01L31/0296 ,  H01L31/0304 ,  H01L31/032 ,  H04N5/33 ,  H04N5/374 ,  H04N9/097 ,  H04N9/76

Abstract: HD color video using monochromatic CMOS image sensors integrated in a 3D package is provided. An example 3DIC package for color video includes a beam splitter to partition received light of an image stream into multiple light outputs. Multiple monochromatic CMOS image sensors are each coupled to one of the multiple light outputs to sense a monochromatic image stream at a respective component wavelength of the received light. Each monochromatic CMOS image sensor is specially constructed, doped, controlled, and tuned to its respective wavelength of light. A parallel processing integrator or interposer chip heterogeneously combines the respective monochromatic image streams into a full-spectrum color video stream, including parallel processing of an infrared or ultraviolet stream. The parallel processing of the monochromatic image streams provides reconstruction to HD or 4K HD color video at low light levels. Parallel processing to one interposer chip also enhances speed, spatial resolution, sensitivity, low light performance, and color reconstruction.