公开(公告)号：US09722053B1

公开(公告)日：2017-08-01

申请号：US15075557

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Hoon Kim ,  Chanro Park ,  Sukwon Hong

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L21/76224 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) while reducing oxidization and fin critical dimension loss. A plurality of fins of a transistor are formed. A hard mask layer is formed on top of the fins. A first liner layer is formed over the fins and the hard mask layer. A partial deposition process is performed for depositing a first insulation material in a first portion of a channel between the fins. A second liner layer is formed above the fins, the first insulation material, and the channel. A second insulation material is deposited above the second liner layer. A fin reveal process is performed for removing the second insulation material to a predetermined height. An etch process is performed for removing the hard mask layer and the first and second liner layers above the predetermined height.

公开(公告)号：US20170207122A1

公开(公告)日：2017-07-20

申请号：US15470006

申请日：2017-03-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Ruilong Xie ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02362 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76837 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2221/1026 ,  H01L2221/1036

Abstract: An integrated circuit product includes two laterally spaced-apart transistors, wherein each of the two laterally spaced-apart transistors includes a gate structure, a gate cap layer positioned above the gate structure, and a sidewall spacer positioned adjacent to sidewalls of the gate structure. A source/drain region is positioned between the two laterally spaced-apart transistors, and a conformal etch stop layer is positioned on and in contact with an upper surface of the source/drain region and on and in contact with a sidewall surface of the sidewall spacer of each of the two laterally spaced-apart transistors. A self-aligned conductive contact extends through an opening in the conformal etch stop layer and is conductively coupled to the source/drain region.

公开(公告)号：US09589836B1

公开(公告)日：2017-03-07

申请号：US15067365

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Hoon Kim

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L21/76843 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329

Abstract: One illustrative method disclosed herein includes, among other things, forming a first conductive structure and a second conductive structure that is conductively coupled to the first conductive structure. In this example, forming the second conductive structure includes forming a ruthenium cap layer on and in contact with an upper surface of the first conductive structure, with the ruthenium cap layer in position, forming a liner layer comprising manganese on and in contact with at least the surfaces of the second layer of insulating material, wherein an upper surface of the ruthenium cap layer is substantially free of the liner layer, and forming a bulk ruthenium material on and in contact with the liner layer, wherein a bottom surface of the bulk ruthenium material contacts the upper surface of the ruthenium cap layer.

Abstract translation: 本文公开的一种说明性方法尤其包括形成导电耦合到第一导电结构的第一导电结构和第二导电结构。 在该实施例中，形成第二导电结构包括在第一导电结构的上表面上形成钌帽层，并将钌盖层置于适当位置，形成在至少与 所述第二绝缘材料层的表面，其中所述钌覆盖层的上表面基本上不含所述衬里层，并且在所述衬里层上形成和接触所述衬层，并且在所述衬底层中形成本体钌材料，其中所述本体钌的底表面 材料接触钌盖层的上表面。

公开(公告)号：US09502286B2

公开(公告)日：2016-11-22

申请号：US14674460

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Andre Labonte

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/283 ,  H01L29/66 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L21/76843 ,  H01L21/283 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66628

Abstract: One method disclosed includes, among other things, forming a structure comprised of an island of a first insulating material positioned between the gate structures above the source/drain region and under a masking layer feature of a patterned masking layer, forming a liner layer that contacts the island of insulating material and the masking layer feature, selectively removing the masking layer feature to thereby form an initial opening that is defined by the liner layer, performing at least one isotropic etching process through the initial opening to remove the island of first insulating material and thereby define a contact opening that exposes the source/drain region, and forming a conductive contact structure in the contact opening that is conductively coupled to the source/drain region.

Abstract translation: 所公开的一种方法包括形成由位于源/漏区之上的栅极结构之间的第一绝缘材料的岛和图案化掩模层的掩模层特征之下的一个结构，形成接触 绝缘材料岛和掩模层特征，选择性地去除掩模层特征，从而形成由衬里层限定的初始开口，通过初始开口进行至少一个各向同性蚀刻工艺以去除第一绝缘材料岛 从而限定暴露源极/漏极区域的接触开口，以及在与源极/漏极区域导电耦合的接触开口中形成导电接触结构。

公开(公告)号：US09484449B2

公开(公告)日：2016-11-01

申请号：US14467357

申请日：2014-08-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Rohit Galatage ,  Hoon Kim

IPC: H01L29/78 ,  H01L21/283 ,  H01L21/28 ,  H01L29/51 ,  H01L29/165

CPC classification number: H01L29/78 ,  H01L21/28158 ,  H01L21/28255 ,  H01L21/283 ,  H01L29/165 ,  H01L29/513 ,  H01L29/517

Abstract: Integrated circuits with a diffusion barrier layers, and processes for preparing integrated circuits including diffusion barrier layers are provided herein. An exemplary integrated circuit includes a semiconductor substrate comprising a semiconductor material, a compound gate dielectric overlying the semiconductor substrate, and a gate electrode overlying the compound gate dielectric. In this embodiment, the compound gate dielectric includes a first dielectric layer, a diffusion barrier layer overlying the first dielectric layer; and a second dielectric layer overlying the diffusion barrier layer; wherein the diffusion barrier layer is made of a material that is less susceptible to diffusion of the semiconductor material than the first dielectric layer, less susceptible to diffusion of oxygen than the second dielectric layer, or both.

Abstract translation: 具有扩散阻挡层的集成电路，以及用于制备包括扩散阻挡层的集成电路的方法。 示例性集成电路包括半导体衬底，其包括半导体材料，覆盖半导体衬底的复合栅极电介质和覆盖复合栅极电介质的栅电极。 在该实施例中，复合栅极电介质包括第一介电层，覆盖第一介电层的扩散阻挡层; 以及覆盖所述扩散阻挡层的第二电介质层; 其中所述扩散阻挡层由比所述第一电介质层更不易受半导体材料扩散影响的材料制成，不如第二电介质层易受氧扩散的影响，或两者兼而有之。

公开(公告)号：US09478538B1

公开(公告)日：2016-10-25

申请号：US14820661

申请日：2015-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Ruilong Xie ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L29/423 ,  H01L21/283

CPC classification number: H01L27/088 ,  H01L21/28088 ,  H01L21/283 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method includes forming first and second gate cavities so as to expose first and second portions of a semiconductor material. A gate insulation layer is formed in the first and second gate cavities. A first work function material layer is formed in the first gate cavity. A second work function material layer is formed in the second gate cavity. A first barrier layer is selectively formed above the first work function material layer and the gate insulation layer in the first gate cavity. A second barrier layer is formed above the first barrier layer in the first gate cavity and above the second work function material layer and the gate insulation layer in the second gate cavity. A conductive material is formed above the second barrier layer in the first and second gate cavities in the presence of a treatment species to define first and second gate electrode structures.

Abstract translation: 一种方法包括形成第一和第二栅极腔以暴露半导体材料的第一和第二部分。 栅极绝缘层形成在第一和第二栅极腔中。 第一工作功能材料层形成在第一浇口腔中。 第二工作功能材料层形成在第二浇口腔中。 第一栅极层选择性地形成在第一栅极腔上的第一功函数材料层和栅极绝缘层之上。 第二势垒层形成在第一栅极腔中的第一势垒层上方，并且在第二栅极腔中的第二功函数材料层和栅极绝缘层之上。 在存在处理物质的情况下，在第一和第二栅极腔中的第二阻挡层上方形成导电材料，以限定第一和第二栅电极结构。

公开(公告)号：US09425106B1

公开(公告)日：2016-08-23

申请号：US14674108

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC: H01L21/308 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L21/823821 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a plurality of fins above a substrate. At least one dielectric material is formed above and between the plurality of fins. A mask layer is formed above the dielectric material. The mask layer has an opening defined therein. A portion of the at least one dielectric material exposed by the opening is removed to expose top and sidewall surface portions of at least a subset of the fins. An etching process is performed to remove the portions of the fins in the subset exposed by removing the portion of the at least one dielectric material.

Abstract translation: 一种方法包括在衬底上形成多个翅片。 在多个翅片之上和之间形成至少一个电介质材料。 在电介质材料上形成掩模层。 掩模层具有限定在其中的开口。 去除由开口暴露的至少一个电介质材料的一部分，以暴露散热片的至少一个子集的顶部和侧壁表面部分。 执行蚀刻工艺以去除通过去除至少一种电介质材料的部分而暴露的子集中的散热片的部分。

公开(公告)号：US20160204034A1

公开(公告)日：2016-07-14

申请号：US14687203

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/308 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306

CPC classification number: H01L21/823412 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211

Abstract: A method includes providing a semiconductor structure including a substrate that includes a material to be patterned. First and second mandrels are formed over the substrate using a common photolithography process that defines a position of the first mandrel relative to the substrate and a position of the second mandrel relative to the substrate. A first sidewall spacer is formed adjacent the first mandrel and a second sidewall spacer is formed adjacent the second mandrel. After the formation of the first and the second sidewall spacers, the first mandrel is removed. The second mandrel remains in the semiconductor structure. A first mask element is provided on the basis of the first sidewall spacer. A second mask element is provided on the basis of the second mandrel and the second sidewall spacer. The material to be patterned is patterned on the basis of the first and the second mask elements.

Abstract translation: 一种方法包括提供包括包括待图案化材料的衬底的半导体结构。 使用公共光刻工艺在衬底上形成第一和第二心轴，其定义第一心轴相对于衬底的位置和第二心轴相对于衬底的位置。 与第一心轴相邻地形成第一侧壁间隔件，并且邻近第二心轴形成第二侧壁间隔件。 在形成第一和第二侧壁间隔物之后，移除第一心轴。 第二心轴保持在半导体结构中。 基于第一侧壁间隔件提供第一掩模元件。 基于第二心轴和第二侧壁间隔件提供第二掩模元件。 基于第一和第二掩模元件对待构图的材料进行图案化。

公开(公告)号：US09379017B1

公开(公告)日：2016-06-28

申请号：US14687203

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie

IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L21/823412 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211

Abstract: A method includes providing a semiconductor structure including a substrate that includes a material to be patterned. First and second mandrels are formed over the substrate using a common photolithography process that defines a position of the first mandrel relative to the substrate and a position of the second mandrel relative to the substrate. A first sidewall spacer is formed adjacent the first mandrel and a second sidewall spacer is formed adjacent the second mandrel. After the formation of the first and the second sidewall spacers, the first mandrel is removed. The second mandrel remains in the semiconductor structure. A first mask element is provided on the basis of the first sidewall spacer. A second mask element is provided on the basis of the second mandrel and the second sidewall spacer. The material to be patterned is patterned on the basis of the first and the second mask elements.

Abstract translation: 一种方法包括提供包括包括待图案化材料的衬底的半导体结构。 使用公共光刻工艺在衬底上形成第一和第二心轴，其定义第一心轴相对于衬底的位置和第二心轴相对于衬底的位置。 与第一心轴相邻地形成第一侧壁间隔件，并且邻近第二心轴形成第二侧壁间隔件。 在形成第一和第二侧壁间隔物之后，移除第一心轴。 第二心轴保持在半导体结构中。 基于第一侧壁间隔件提供第一掩模元件。 基于第二心轴和第二侧壁间隔件提供第二掩模元件。 基于第一和第二掩模元件对待构图的材料进行图案化。

公开(公告)号：US09337101B1

公开(公告)日：2016-05-10

申请号：US14674549

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Hoon Kim ,  Chanro Park ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/823431 ,  H01L21/3083 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823481

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of fins in a semiconducting substrate, each of which has a corresponding masking layer feature positioned thereabove, forming a masking layer that has an opening that exposes at least two fins of the plurality of fins, performing an angled etching process through the opening in the masking layer so as to remove the masking layer feature formed above one of the at least two exposed fins, and thereby define an exposed fin, while leaving the masking layer feature intact above the other of the at least two exposed fins, and performing an anisotropic etching process through the opening in the masking layer to remove the exposed fin while leaving the other of the at least two exposed fins intact.

Abstract translation: 本文中公开的一种说明性方法包括在半导体衬底中形成多个翅片，每个鳍状物具有位于其上方的对应掩模层特征，形成掩模层，掩模层具有暴露至少两个散热片的开口 的翅片，通过掩模层中的开口进行成角度的蚀刻工艺，以去除在至少两个暴露的翅片之一上形成的掩模层特征，从而限定出露出的翅片，同时将掩模层特征保留在 至少两个暴露的翅片中的另一个，并且通过掩模层中的开口进行各向异性蚀刻处理以去除暴露的翅片，同时保持至少两个暴露的翅片中的另一个。