公开(公告)号：US20230378931A1

公开(公告)日：2023-11-23

申请号：US18352972

申请日：2023-07-14

Applicant: Soitec

Inventor： Marcel Broekaart ,  Thierry Barge ,  Pascal Guenard ,  Ionut Radu ,  Eric Desbonnets ,  Oleg Kononchuk

IPC: H03H9/02 ,  H03H3/02 ,  H03H9/17 ,  H03H9/145 ,  H10N30/072 ,  H10N30/87 ,  H03H9/64 ,  A61B5/00 ,  H03H9/25 ,  H03H9/56 ,  A61B5/145 ,  A61B5/1459 ,  H03H3/04 ,  H03H9/13 ,  H10N39/00 ,  H03H3/10 ,  H10N30/085

CPC classification number: H03H9/02834 ,  H03H3/02 ,  H03H9/02102 ,  H03H9/17 ,  H03H9/145 ,  H10N30/072 ,  H10N30/87 ,  H03H9/6489 ,  A61B5/685 ,  H03H9/25 ,  H03H9/56 ,  A61B5/14546 ,  A61B5/1459 ,  H03H3/04 ,  H03H9/13 ,  H03H9/02574 ,  H10N39/00 ,  H03H3/10 ,  H10N30/085 ,  H03H2003/0407 ,  A61B2562/0204

Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.

公开(公告)号：US20220277988A1

公开(公告)日：2022-09-01

申请号：US17663898

申请日：2022-05-18

Applicant: Soitec

Inventor： Eric Desbonnets ,  Ionut Radu ,  Oleg Kononchuk ,  Jean-Pierre Raskin

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02 ,  H01L29/786 ,  H01L29/06

Abstract: Substrates for microelectronic radiofrequency devices may include a substrate comprising a semiconductor material. Trenches may be located in an upper surface of the substrate, at least some of the trenches including a filler material located within the respective trench. A resistivity of the filler material may be 10 kOhms·cm or greater. A piezoelectric material may be located on or above the upper surface of the substrate. Methods of making substrates for microelectronic radiofrequency devices may involve forming trenches in an upper surface of a substrate including a semiconductor material. A filler material may be placed in at least some of the trenches, and a piezoelectric material may be placed on or above the upper surface of the substrate.

公开(公告)号：US20210121103A1

公开(公告)日：2021-04-29

申请号：US17141065

申请日：2021-01-04

Applicant: Soitec

Inventor： Marcel Broekaart ,  Thierry Barge ,  Pascal Guenard ,  Ionut Radu ,  Eric Desbonnets ,  Oleg Kononchuk

IPC: A61B5/1459 ,  A61B5/00 ,  A61B5/145

Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.

公开(公告)号：US20210118717A1

公开(公告)日：2021-04-22

申请号：US17135340

申请日：2020-12-28

Applicant: Soitec

Inventor： Marcel Broekaart ,  Ionut Radu ,  Didier Landru

IPC: H01L21/683 ,  H01L21/48 ,  H01L21/762

Abstract: The present disclosure relates to a method for mechanically separating layers, in particular in a double layer transfer process. The present disclosure relates more in particular to a method for mechanically separating layers, comprising the steps of providing a semiconductor compound comprising a layer of a handle substrate and an active layer with a front main side and a back main side opposite the front main side, wherein the layer of the handle substrate is attached to the front main side of the active layer, then providing a layer of a carrier substrate onto the back main side of the active layer, and then initiating mechanical separation of the layer of the handle substrate, wherein the layer of the handle substrate and the layer of the carrier substrate are provided with a substantially symmetrical mechanical structure.

公开(公告)号：US10276492B2

公开(公告)日：2019-04-30

申请号：US15405867

申请日：2017-01-13

Applicant: Soitec

Inventor： Ionut Radu ,  Eric Desbonnets

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/66 ,  H01L21/762

Abstract: Methods of forming a semiconductor structure include forming a device layer on an initial substrate, attaching a first surface of the device layer to a temporary substrate and forming a high resistivity layer on a second surface of the device layer by removing a portion of the initial substrate. Methods further include attaching a final substrate to the high resistivity layer and removing the temporary substrate. Semiconductor structures are fabricated by such methods that include a final substrate, a high resistivity layer disposed over the final substrate and a device layer disposed over the high resistivity layer.

公开(公告)号：US20180159498A1

公开(公告)日：2018-06-07

申请号：US15735477

申请日：2016-06-09

Applicant: Soitec

Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

IPC: H03H9/02 ,  H03H3/10

Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

公开(公告)号：US09553014B2

公开(公告)日：2017-01-24

申请号：US14694794

申请日：2015-04-23

Applicant: Soitec

Inventor： Mariam Sadaka ,  Ionut Radu

IPC: H01L21/30 ,  H01L21/762 ,  H01L21/20 ,  H01L21/683 ,  H01L21/768 ,  H01L25/00 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L21/76254 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/98 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/03616 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08121 ,  H01L2224/08146 ,  H01L2224/0903 ,  H01L2224/16145 ,  H01L2224/27444 ,  H01L2224/27616 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80 ,  H01L2224/80006 ,  H01L2224/80011 ,  H01L2224/80121 ,  H01L2224/802 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80805 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80905 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83011 ,  H01L2224/83022 ,  H01L2224/83121 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/832 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83805 ,  H01L2224/83896 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3512

Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

Abstract translation: 制造半导体结构的方法包括将原子物质注入到载体晶粒或晶片中以在载体晶粒或晶片内形成弱化区域，并将载体晶片或晶片结合到半导体结构。 可以在使用载体晶片或晶片来处理半导体结构的同时对半导体结构进行处理。 半导体结构可以结合到另一个半导体结构，并且载体晶片或晶片可以沿其中的弱化区域分割。 使用这种方法制造粘合的半导体结构。

公开(公告)号：US20160197006A1

公开(公告)日：2016-07-07

申请号：US14903961

申请日：2014-06-24

Applicant: SOITEC

Inventor： Marcel Broekaart ,  Ionut Radu ,  Chrystelle Lagahe Blanchard

IPC: H01L21/762 ,  H01L23/544

CPC classification number: H01L21/76254 ,  H01L23/544 ,  H01L27/14687 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosure relates to a process for locating devices, the process comprising the following steps: a) providing a carrier substrate comprising: a device layer; and alignment marks; b) providing a donor substrate; c) forming a weak zone in the donor substrate, the weak zone delimiting a useful layer; d) assembling the donor substrate and the carrier substrate; and e) fracturing the donor substrate in the weak zone so as to transfer the useful layer to the device layer; wherein the alignment marks are placed in cavities formed in the device layer, the cavities having an aperture flush with the free surface of the device layer.

Abstract translation: 本公开涉及一种用于定位设备的方法，该方法包括以下步骤：a）提供载体衬底，其包括：器件层; 和对准标记; b）提供供体底物; c）在施主衬底中形成弱区，限定有用层的弱区; d）组装供体衬底和载体衬底; 以及e）在所述弱区中破坏所述施主衬底，以将所述有用层转移到所述器件层; 其中对准标记被放置在形成在器件层中的空腔中，空腔具有与器件层的自由表面齐平的孔。

公开(公告)号：US09138980B2

公开(公告)日：2015-09-22

申请号：US13624470

申请日：2012-09-21

Applicant: Soitec

Inventor： Marcel Broekaart ,  Ionut Radu

IPC: B32B37/10 ,  B32B38/18 ,  H01L21/67

CPC classification number: H01L25/50 ,  B32B38/1858 ,  B32B2309/64 ,  B32B2309/65 ,  B32B2309/68 ,  H01L21/67092 ,  H01L2924/0002 ,  Y10T156/10 ,  H01L2924/00

Abstract: The present invention relates to an apparatus for the manufacture of semiconductor devices wherein the apparatus includes a bonding module that has a vacuum chamber to provide bonding of wafers under pressure below atmospheric pressure; and a loadlock module connected to the bonding module and configured for wafer transfer to the bonding module. The loadlock module is also connected to a first vacuum pumping device configured to reduce the pressure in the loadlock module to below atmospheric pressure. The bonding and loadlock modules remain at a pressure below atmospheric pressure while the wafer is transferred from the loadlock module into the bonding module.

Abstract translation: 本发明涉及一种用于制造半导体器件的装置，其中所述装置包括具有真空室的接合模块，以在低于大气压的压力下提供晶片的接合; 以及负载锁模块，其连接到所述接合模块并且被配置为用于晶片转移到所述接合模块。 负载锁模块还连接到第一真空泵装置，其被配置成将负载锁模块中的压力降低到低于大气压。 接合和负载锁定模块保持在低于大气压力的压力下，同时晶片从负载锁定模块传输到接合模块中。

公开(公告)号：US20150228535A1

公开(公告)日：2015-08-13

申请号：US14694794

申请日：2015-04-23

Applicant: SOITEC

Inventor： Mariam Sadaka ,  Ionut Radu

IPC: H01L21/762 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L21/76254 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/98 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/03616 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08121 ,  H01L2224/08146 ,  H01L2224/0903 ,  H01L2224/16145 ,  H01L2224/27444 ,  H01L2224/27616 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80 ,  H01L2224/80006 ,  H01L2224/80011 ,  H01L2224/80121 ,  H01L2224/802 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80805 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80905 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83011 ,  H01L2224/83022 ,  H01L2224/83121 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/832 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83805 ,  H01L2224/83896 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3512

Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

Abstract translation: 制造半导体结构的方法包括将原子物质注入到载体晶粒或晶片中以在载体晶粒或晶片内形成弱化区域，并将载体晶片或晶片结合到半导体结构。 可以在使用载体晶片或晶片来处理半导体结构的同时对半导体结构进行处理。 半导体结构可以结合到另一个半导体结构，并且载体晶片或晶片可以沿其中的弱化区域分割。 使用这种方法制造粘合的半导体结构。