公开(公告)号：US20170341201A1

公开(公告)日：2017-11-30

申请号：US15165902

申请日：2016-05-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wei Hsu ,  Chi-Jen Liu ,  Liang-Guang Chen ,  Chih-Chung Chang ,  Cheng-Chun Chang ,  Hsin-Kai Chen ,  Yi-Sheng Lin ,  Shi-Ya Hsu ,  Tsung-Ju Lin ,  Yi-Sheng Ma

IPC: B24B37/32 ,  B24B37/20

CPC classification number: B24B37/32 ,  B24B37/20

Abstract: An embodiment retainer ring includes an outer ring encircling an opening and an inner ring attached to the outer ring. The inner ring is disposed between the opening and the outer ring. The inner ring includes a softer material than the outer ring and a plurality of voids within the softer material.

公开(公告)号：US20170221700A1

公开(公告)日：2017-08-03

申请号：US15492034

申请日：2017-04-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Li-Chieh Wu ,  Chi-Jen Liu ,  He Hui Peng ,  Liang-Guang Chen ,  Yung-Chung Chen

IPC: H01L21/02 ,  H01L21/288 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/02068 ,  H01L21/02063 ,  H01L21/0234 ,  H01L21/28079 ,  H01L21/28132 ,  H01L21/288 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L29/401 ,  H01L29/66545

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

公开(公告)号：US20170092481A1

公开(公告)日：2017-03-30

申请号：US14870946

申请日：2015-09-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fu-Ming Huang ,  Liang-Guang Chen ,  Ting-Kui Chang ,  Chun-Chieh Lin

IPC: H01L21/02 ,  B08B1/04 ,  H01L21/67 ,  H01L21/306 ,  H01L21/687 ,  B08B1/00 ,  B08B3/04

CPC classification number: H01L21/02043 ,  B08B1/002 ,  B08B1/04 ,  B08B3/04 ,  H01L21/02065 ,  H01L21/02074 ,  H01L21/30625 ,  H01L21/67028 ,  H01L21/67046 ,  H01L21/67092 ,  H01L21/687

Abstract: A method includes performing a first post Chemical Mechanical Polish (CMP) cleaning on a wafer using a first brush. The first brush rotates to clean the wafer. The method further includes performing a second post-CMP cleaning on the wafer using a second brush. The second brush rotates to clean the wafer. The first post-CMP cleaning and the second post-CMP cleaning are performed simultaneously.

公开(公告)号：US09449841B2

公开(公告)日：2016-09-20

申请号：US14134914

申请日：2013-12-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Chi-Jen Liu ,  Ying-Liang Chuang ,  Li-Chieh Wu ,  Liang-Guang Chen ,  Ming-Liang Yen

IPC: H01L21/02 ,  H01L21/321 ,  H01L29/66 ,  H01L21/67

CPC classification number: H01L21/28123 ,  B24B37/20 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/67051 ,  H01L29/66545

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor structure including a metal gate (MG) layer formed to fill in a trench between two adjacent interlayer dielectric (ILD) regions; performing a chemical mechanical polishing (CMP) process using a CMP system to planarize the MG layer and the ILD regions; and cleaning the planarized MG layer using a O3/DIW solution including ozone gas (O3) dissolved in deionized water (DIW). The MG layer is formed on the ILD regions.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供包括形成为填充两个相邻层间电介质（ILD）区域之间的沟槽的金属栅极（MG）层的半导体结构; 使用CMP系统进行化学机械抛光（CMP）处理以使MG层和ILD区域平坦化; 以及使用溶解在去离子水（DIW）中的包含臭氧气体（O 3）的O 3 / DIW溶液清洗平坦化的MG层。 MG层形成在ILD区域上。

公开(公告)号：US09209272B2

公开(公告)日：2015-12-08

申请号：US14024247

申请日：2013-09-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Jen Liu ,  Li-Chieh Wu ,  Shich-Chang Suen ,  Liang-Guang Chen

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/02074 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76895 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

Abstract: A method includes forming a dummy gate of a transistor at a surface of a wafer, removing the dummy gate, and filling a metallic material into a trench left by the removed dummy gate. A Chemical Mechanical Polish (CMP) is then performed on the metallic material, wherein a remaining portion of the metallic material forms a metal gate of the transistor. After the CMP, a treatment is performed on an exposed top surface of the metal gate using an oxidation-and-etching agent comprising chlorine and oxygen.

Abstract translation: 一种方法包括在晶片的表面上形成晶体管的虚拟栅极，去除虚拟栅极，并将金属材料填充到由去除的虚拟栅极留下的沟槽中。 然后对金属材料进行化学机械抛光（CMP），其中金属材料的剩余部分形成晶体管的金属栅极。 在CMP之后，使用包含氯和氧的氧化 - 蚀刻剂在金属栅极的暴露的顶表面上进行处理。

公开(公告)号：US20150179432A1

公开(公告)日：2015-06-25

申请号：US14134914

申请日：2013-12-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Chi-Jen Liu ,  Ying-Liang Chuang ,  Li-Chieh Wu ,  Liang-Guang Chen ,  Ming-Liang Yen

IPC: H01L21/02 ,  H01L21/306

CPC classification number: H01L21/28123 ,  B24B37/20 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/67051 ,  H01L29/66545

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor structure including a metal gate (MG) layer formed to fill in a trench between two adjacent interlayer dielectric (ILD) regions; performing a chemical mechanical polishing (CMP) process using a CMP system to planarize the MG layer and the ILD regions; and cleaning the planarized MG layer using a O3/DIW solution including ozone gas (O3) dissolved in deionized water (DIW). The MG layer is formed on the ILD regions.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供包括形成为填充两个相邻层间电介质（ILD）区域之间的沟槽的金属栅极（MG）层的半导体结构; 使用CMP系统进行化学机械抛光（CMP）处理以使MG层和ILD区域平坦化; 以及使用溶解在去离子水（DIW）中的包含臭氧气体（O 3）的O 3 / DIW溶液清洗平坦化的MG层。 MG层形成在ILD区域上。

公开(公告)号：US12297375B2

公开(公告)日：2025-05-13

申请号：US17141988

申请日：2021-01-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ji Cui ,  Chi-Jen Liu ,  Liang-Guang Chen ,  Kei-Wei Chen ,  Chun-Wei Hsu ,  Li-Chieh Wu ,  Peng-Chung Jangjian ,  Kao-Feng Liao ,  Fu-Ming Huang ,  Wei-Wei Liang ,  Tang-Kuei Chang ,  Hui-Chi Huang

IPC: C09G1/02 ,  H01L21/321 ,  H01L21/768 ,  H01L23/535

Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one rheology modifier. The slurry includes at least one liquid carrier, at least one abrasives and at least one oxidizer. The rheology modifier is dispensed in the slurry. The polishing method includes using the slurry composition with the rheology modifier to polish a conductive layer.

公开(公告)号：US12131944B2

公开(公告)日：2024-10-29

申请号：US17460929

申请日：2021-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun-Wei Hsu ,  Chih-Chieh Chang ,  Yi-Sheng Lin ,  Jian-Ci Lin ,  Jeng-Chi Lin ,  Ting-Hsun Chang ,  Liang-Guang Chen ,  Ji Cui ,  Kei-Wei Chen ,  Chi-Jen Liu

IPC: H01L21/768 ,  C09G1/02 ,  H01L23/522

CPC classification number: H01L21/7684 ,  C09G1/02 ,  H01L21/76877 ,  H01L23/5226

Abstract: A slurry composition, a semiconductor structure and a method for forming a semiconductor structure are provided. The slurry composition includes a slurry and a precipitant dispensed in the slurry. The semiconductor structure comprises a blocking layer including at least one element of the precipitant. The method includes using the slurry composition with the precipitant to polish a conductive layer and causing the precipitant to flow into the gap.

公开(公告)号：US12002684B2

公开(公告)日：2024-06-04

申请号：US18057728

申请日：2022-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ji Cui ,  Fu-Ming Huang ,  Ting-Kui Chang ,  Tang-Kuei Chang ,  Chun-Chieh Lin ,  Wei-Wei Liang ,  Liang-Guang Chen ,  Kei-Wei Chen ,  Hung Yen ,  Ting-Hsun Chang ,  Chi-Hsiang Shen ,  Li-Chieh Wu ,  Chi-Jen Liu

IPC: H01L21/321 ,  B24B37/04 ,  B24B37/10 ,  C09G1/02

CPC classification number: H01L21/3212 ,  B24B37/044 ,  B24B37/107 ,  C09G1/02

Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.

公开(公告)号：US11996283B2

公开(公告)日：2024-05-28

申请号：US17874152

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Li-Chieh Wu ,  Chi-Jen Liu ,  He Hui Peng ,  Liang-Guang Chen ,  Yung-Chung Chen

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/288 ,  H01L21/311 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L21/02068 ,  H01L21/02063 ,  H01L21/0234 ,  H01L21/28079 ,  H01L21/28132 ,  H01L21/288 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L29/40114 ,  H01L29/66545

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.