公开(公告)号：US20140361420A1

公开(公告)日：2014-12-11

申请号：US13913770

申请日：2013-06-10

Applicant: Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu ,  Peter Wilson ,  Yan Huo ,  Zhiqiang Niu ,  Ming-Chen Lu

Inventor： Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu ,  Peter Wilson ,  Yan Huo ,  Zhiqiang Niu ,  Ming-Chen Lu

IPC: H01L23/495

CPC classification number: H01L23/49568 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/565 ,  H01L21/768 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/544 ,  H01L24/40 ,  H01L24/41 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/5446 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/06181 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/73104 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/27 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.

Abstract translation: 一种混合封装多芯片半导体器件，包括引线框单元，第一半导体芯片，第二半导体芯片，第一互连结构和第二互连结构，其中第一半导体芯片附接在第一裸片上，第二半导体 芯片被翻转并附接在第三引脚和第二管芯焊盘上，第一互连结构电连接第一半导体芯片的前表面处的第一电极和第二半导体芯片的后表面处的第三电极和第二电极 在第一半导体芯片的前表面通过第二互连结构电连接。

公开(公告)号：US08877555B2

公开(公告)日：2014-11-04

申请号：US13678847

申请日：2012-11-16

Applicant: Lei Shi ,  Yan Xun Xue ,  Yuping Gong

Inventor： Lei Shi ,  Yan Xun Xue ,  Yuping Gong

IPC: H01L21/56 ,  H01L23/00

CPC classification number: H01L21/561 ,  H01L21/4832 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49582 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92247 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected.

Abstract translation: 公开了专门用于倒装芯片垂直功率器件的封装半导体器件的制备方法。 在这些方法中，将垂直半导体芯片倒装芯片连接到引线框架，然后用塑料包装材料封装。 然后将封装的芯片变薄到预定厚度。 通过蚀刻至少连接的引线框架的底部部分，形成连接芯片与外部电路的接触端子。

公开(公告)号：US20140319601A1

公开(公告)日：2014-10-30

申请号：US13871144

申请日：2013-04-26

Applicant: Yueh-Se Ho ,  Yan Xun Xue ,  Ping Huang

Inventor： Yueh-Se Ho ,  Yan Xun Xue ,  Ping Huang

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L29/42372 ,  H01L29/781 ,  H01L2224/04105 ,  H01L2224/05016 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/051 ,  H01L2224/05562 ,  H01L2224/06102 ,  H01L2224/06181 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

Abstract: A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface.

Abstract translation: 底部源极功率金属氧化物半导体场效应晶体管（MOSFET）器件包括形成在半导体芯片的第一表面上的初始绝缘层上的栅电极和源电极，以及形成在半导体芯片的第二表面上的漏电极 半导体芯片 源电极包括源极金属，形成在源极金属上的源极电极凸点和源极电极凸起顶部上的源电极金属层。 第一绝缘层覆盖栅电极。 从芯片的第二表面形成与栅电极对准的贯通孔，以将栅电极的一部分从第二表面露出。

公开(公告)号：US08785296B2

公开(公告)日：2014-07-22

申请号：US13396531

申请日：2012-02-14

Applicant: Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho

Inventor： Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho

IPC: H01L21/46 ,  H01L21/00

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/94 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00015

Abstract: A packaging method with backside wafer dicing includes the steps of forming a support structure at the front surface of the wafer then depositing a metal layer on a center area of the backside of the wafer after grinding the wafer backside to reduce the wafer thickness; detecting from the backside of the wafer sections of scribe lines formed in the front surface in the region between the edge of the metal layer and the edge of the wafer and cutting the wafer and the metal layer from the wafer backside along a straight line formed by extending a scribe line section detected from the wafer backside.

Abstract translation: 具有背面晶片切割的封装方法包括以下步骤：在晶片的前表面形成支撑结构，然后在晶片背面研磨之后在晶片背面的中心区域沉积金属层以减小晶片厚度; 从形成在金属层的边缘与晶片边缘之间的区域中的前表面的划线的背面检测，并从晶片背面沿着直线形成的直线切割晶片和金属层， 延伸从晶片背面检测的划线部分。

公开(公告)号：US08722467B2

公开(公告)日：2014-05-13

申请号：US13539304

申请日：2012-06-30

Applicant: Lei Shi ,  Aihua Lu ,  Yan Xun Xue

Inventor： Lei Shi ,  Aihua Lu ,  Yan Xun Xue

IPC: H01L21/50 ,  H01L21/60 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L21/50 ,  H01L23/495 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/14 ,  H01L24/17 ,  H01L24/32 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/8314 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A die attach method for a semiconductor chip with a back metal layer located at the back surface of the semiconductor chip comprises the steps of forming a bonding ball array including a plurality of bonding balls with a same height on a die attach area at a top surface of a die paddle; depositing a die attach material in the bonding ball array area with a thickness of the die attach material equal or slightly larger than the height of the bonding ball; attaching the semiconductor chip to the die attach area at the top surface of the die paddle by the die attach material, wherein the bonding ball array controls the bond line thickness of the die attach material between the back metal layer and the top surface of the die paddle and prevents the semiconductor chip from rotating on the die attach material when it is melted.

Abstract translation: 具有位于半导体芯片的背面的背面金属层的半导体芯片的芯片贴附方法包括以下步骤：在上表面的芯片附着区域上形成包括具有相同高度的多个接合球的接合球阵列 的模具 在焊接球阵列区域中沉积管芯附着材料，其中管芯附着材料的厚度等于或略大于焊接球的高度; 将所述半导体芯片通过所述芯片附着材料附接到所述芯片的顶表面处的所述芯片附着区域，其中，所述接合球阵列控制所述芯片附着材料在所述背面金属层与所述模具的顶表面之间的结合线厚度 并且防止半导体芯片在熔融时在芯片附着材料上旋转。

公开(公告)号：US08703545B2

公开(公告)日：2014-04-22

申请号：US13408185

申请日：2012-02-29

Applicant: Zhiqiang Niu ,  Ming-Chen Lu ,  Yan Xun Xue ,  Yan Huo ,  Hua Pan ,  Guo Feng Lian ,  Jun Lu

Inventor： Zhiqiang Niu ,  Ming-Chen Lu ,  Yan Xun Xue ,  Yan Huo ,  Hua Pan ,  Guo Feng Lian ,  Jun Lu

IPC: H01L21/56 ,  H01L23/495

CPC classification number: H01L23/3107 ,  H01L21/565 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/73 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor package is provided with an Aluminum alloy lead-frame without noble metal plated on the Aluminum base lead-frame. Aluminum alloy material with proper alloy composition and ratio for making an aluminum alloy lead-frame is provided. The aluminum alloy lead-frame is electroplated with a first metal electroplating layer, a second electroplating layer and a third electroplating layer in a sequence. The lead-frame electroplated with the first, second and third metal electroplating layers is then used in the fabrication process of a power semiconductor package including chip connecting, wire bonding, and plastic molding. After the molding process, the area of the lead-frame not covered by the molding compound is electroplated with a fourth metal electroplating layer that is not easy to be oxidized when exposing to air.

Abstract translation: 半导体封装设置有没有贵金属的铝合金引线框架，镀在铝基底引线框架上。 提供具有适当的合金组成和制造铝合金引线框架的比例的铝合金材料。 铝合金引线框架依次电镀有第一金属电镀层，第二电镀层和第三电镀层。 然后，利用第一，第二和第三金属电镀层电镀的引线框架用于包括芯片连接，引线接合和塑性模制的功率半导体封装的制造过程中。 在模制过程之后，未被模塑料覆盖的引线框架的区域用暴露于空气中不容易氧化的第四金属电镀层电镀。

公开(公告)号：US08686546B2

公开(公告)日：2014-04-01

申请号：US13077720

申请日：2011-03-31

Applicant: Yueh-Se Ho ,  Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu

Inventor： Yueh-Se Ho ,  Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu

IPC: H01L23/495 ,  H01L23/02

CPC classification number: H01L23/49524 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/84 ,  H01L25/074 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/4118 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2224/85399 ,  H01L2224/92 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/84 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

Abstract: A combined packaged power semiconductor device includes a flipped top source low-side MOSFET electrically connected to a top surface of a die paddle, a first metal interconnection plate connecting between a bottom drain of a high-side MOSFET or a top source of a flipped high-side MOSFET to a bottom drain of the low-side MOSFET, and a second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally that reduces the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.

Abstract translation: 组合封装的功率半导体器件包括电连接到管芯焊盘的顶表面的翻转顶部源极低侧MOSFET，连接在高侧MOSFET的底部漏极或翻转高电平的顶部源的第一金属互连板 的低端MOSFET的底部漏极和堆叠在高侧MOSFET芯片的顶部上的第二金属互连板。 高侧，低端MOSFET和IC控制器可以三维封装，从而减小半导体器件的总体尺寸，并可在相同尺寸的封装内最大限度地提高芯片的尺寸，并提高半导体器件的性能。 翻转的低侧MOSFET的顶部源极连接到管芯焊盘的顶表面，并且因此通过裸片的裸露的底表面接地，这简化了裸片焊盘的暴露的底面的形状，并使面积最大化 散热。

公开(公告)号：US08642385B2

公开(公告)日：2014-02-04

申请号：US13205864

申请日：2011-08-09

Applicant: Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Ming-Chen Lu

Inventor： Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Ming-Chen Lu

IPC: H01L23/498 ,  H01L21/78

CPC classification number: H01L21/76898 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/1184 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The present invention proposes a package for semiconductor device and the fabrication method for integrally encapsulating a whole semiconductor chip within a molding compound. In the semicondcutor device package, bonding pads distributed on the top of the chip are redistributed into an array of redistributed bonding pads located in an dielectric layer by utilizing the redistribution technique. The electrodes or signal terminals on the top of the semiconductor chip are connected to an electrode metal segment on the bottom of the chip by conductive materials filled in through holes formed in a silicon substrate of a semiconductor wafer. Furthermore, the top molding portion and the bottom molding portion seal the semiconductor chip completely, thus providing optimum mechanical and electrical protections.

Abstract translation: 本发明提出了一种用于半导体器件的封装以及用于将整个半导体芯片整体封装在模塑料中的制造方法。 在半封装器件封装中，通过利用再分配技术，分布在芯片顶部的焊盘重新分布到位于介质层中的再分布焊盘的阵列中。 半导体芯片的顶部上的电极或信号端子通过填充在半导体晶片的硅衬底中形成的通孔中的导电材料连接到芯片底部的电极金属段。 此外，顶部模制部分和底部模制部分完全密封半导体芯片，从而提供最佳的机械和电气保护。

公开(公告)号：US20140001617A1

公开(公告)日：2014-01-02

申请号：US13539304

申请日：2012-06-30

Applicant: Lei Shi ,  Aihua Lu ,  Yan Xun Xue

Inventor： Lei Shi ,  Aihua Lu ,  Yan Xun Xue

IPC: H01L21/50 ,  H01L23/495

CPC classification number: H01L24/11 ,  H01L21/50 ,  H01L23/495 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/14 ,  H01L24/17 ,  H01L24/32 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/8314 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A die attach method for a semiconductor chip with a back metal layer located at the back surface of the semiconductor chip comprises the steps of forming a bonding ball array including a plurality of bonding balls with a same height on a die attach area at a top surface of a die paddle; depositing a die attach material in the bonding ball array area with a thickness of the die attach material equal or slightly larger than the height of the bonding ball; attaching the semiconductor chip to the die attach area at the top surface of the die paddle by the die attach material, wherein the bonding ball array controls the bond line thickness of the die attach material between the back metal layer and the top surface of the die paddle and prevents the semiconductor chip from rotating on the die attach material when it is melted.

Abstract translation: 具有位于半导体芯片的背面的背面金属层的半导体芯片的芯片贴附方法包括以下步骤：在上表面的芯片附着区域上形成包括具有相同高度的多个接合球的接合球阵列 的模具 在焊接球阵列区域中沉积管芯附着材料，其中管芯附着材料的厚度等于或略大于焊接球的高度; 将所述半导体芯片通过所述芯片附着材料附接到所述芯片的顶表面处的所述芯片附着区域，其中，所述接合球阵列控制所述芯片附着材料在所述背面金属层与所述模具的顶表面之间的结合线厚度 并且防止半导体芯片在熔融时在芯片附着材料上旋转。

公开(公告)号：US08575006B2

公开(公告)日：2013-11-05

申请号：US12592596

申请日：2009-11-30

Applicant: Yan Xun Xue ,  Jun Lu

Inventor： Yan Xun Xue ,  Jun Lu

IPC: H01L31/00

CPC classification number: H01L23/49551 ,  H01L21/4842 ,  H01L21/561 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: This invention discloses a process for packaging semiconductor device with external leads. The process includes comprises Step 1: providing a lead frame comprising a plurality of lead frame units connected by a plurality of metal beams, each lead frame unit comprising a die pad and a plurality of leads located on opposite sides of the die pad; adhering a semiconductor chip onto each of the die pad, and providing a plurality of metal connections for electrically connecting each chip to its corresponding leads; Step 2 providing a plastic molding material to enclose the plurality of the lead frame units, the metal beams, the chips, and at least portions of the metal connections; Step 3 removing a portion of the plastic molding material above the metal beams to expose the metal beams and portions of the leads in connection with the metal beams; and Step 4 separating each lead frame unit, forming a plurality of individual semiconductor plastic package components with external leads.

Abstract translation: 本发明公开了一种用外部引线封装半导体器件的方法。 该方法包括步骤1：提供引线框架，该引线框架包括由多个金属梁连接的多个引线框架单元，每个引线框架单元包括管芯焊盘和位于管芯焊盘的相对侧上的多个引线; 将半导体芯片粘附到每个芯片焊盘上，并且提供多个金属连接件，用于将每个芯片电连接到其相应的引线; 步骤2提供塑料模制材料以封闭多个引线框架单元，金属梁，芯片以及金属连接件的至少部分; 步骤3，移除金属梁上方的塑料成型材料的一部分，以暴露金属梁和引线的与金属梁相关的部分; 以及步骤4分离每个引线框架单元，用外部引线形成多个单独的半导体塑料封装部件。