公开(公告)号：US20160371187A1

公开(公告)日：2016-12-22

申请号：US14746610

申请日：2015-06-22

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: G06F12/08 ,  G11C7/10 ,  G06F12/06

CPC classification number: G06F12/0862 ,  G06F12/0638 ,  G06F12/0811 ,  G06F12/0835 ,  G06F2212/1016 ,  G06F2212/205 ,  G06F2212/502 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6024 ,  G06F2212/6026 ,  G06F2212/6028 ,  G06F2212/621

Abstract: A plurality of memory modules, which may be used to form a heterogeneous memory system, are connected to a plurality of prefetchers. Each prefetcher is independently configured to prefetch information from a corresponding one of the plurality of memory modules in response to feedback from the corresponding one of the plurality of memory modules.

Abstract translation: 可以用于形成异构存储器系统的多个存储器模块连接到多个预取器。 每个预取器被独立地配置为响应于来自多个存储器模块中的对应的一个的反馈而从多个存储器模块中的对应的一个存储器模块预取信息。

公开(公告)号：US20160335026A1

公开(公告)日：2016-11-17

申请号：US15223347

申请日：2016-07-29

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Shinichi KANNO ,  Kazuhiro FUKUTOMI

IPC: G06F3/06 ,  G11B5/54

CPC classification number: G06F3/0647 ,  G06F3/0619 ,  G06F3/0685 ,  G06F12/0871 ,  G06F2212/222 ,  G06F2212/313 ,  G06F2212/502 ,  G11B5/54

Abstract: According to one embodiment, a data storage device includes a first storage unit, a second storage unit, a first queue, a second queue, and a distributor. The second storage unit is used as a cache of the first storage unit and has a lower write transfer rate and a faster response time than the first storage unit. The first queue corresponds to the first storage unit. The second queue corresponds to the second storage unit. The distributor distributes a write command received presently from a host to one of the first and second queues in which the number of write commands registered presently is smaller.

Abstract translation: 根据一个实施例，数据存储设备包括第一存储单元，第二存储单元，第一队列，第二队列和分发器。 第二存储单元用作第一存储单元的高速缓存，并且具有比第一存储单元更低的写入传送速率和更快的响应时间。 第一个队列对应于第一个存储单元。 第二队列对应于第二存储单元。 分发器将当前从主机接收到的写命令分配到当前登记的写入命令的数量较小的第一和第二队列之一。

公开(公告)号：US09471490B2

公开(公告)日：2016-10-18

申请号：US14840639

申请日：2015-08-31

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F12/00 ,  G06F12/08 ,  G06F1/28

CPC classification number: G06F1/3275 ,  G06F1/28 ,  G06F1/3287 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0848 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/502 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

公开(公告)号：US20160246731A1

公开(公告)日：2016-08-25

申请号：US14626925

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward KOOB ,  Erich James PLONDKE ,  Jiajin TU

IPC: G06F12/10 ,  G06F11/07

CPC classification number: G06F12/1027 ,  G06F1/32 ,  G06F11/073 ,  G06F11/079 ,  G06F12/08 ,  G06F2212/1028 ,  G06F2212/1032 ,  G06F2212/502 ,  G06F2212/684 ,  Y02D10/13

Abstract: A translation lookaside buffer (TLB) stores translation entries. The translation entries include a virtual address, a physical address and a memory local/not-local flag. When a processor is in a low power/local memory mode a virtual address is received. A matching translation entry has a local/not-local flag. Upon the local/not-local flag indicating the physical address of the matching translation entry being outside the local memory, an out-of-access-range memory access exception is generated.

Abstract translation: 翻译后备缓冲器（TLB）存储翻译条目。 翻译条目包括虚拟地址，物理地址和存储器本地/非本地标志。 当处理器处于低功耗/本地存储器模式时，接收到虚拟地址。 匹配的翻译条目具有本地/非本地标志。 在指示本地存储器外的匹配转换条目的物理地址的本地/非本地标志时，生成访问范围外存储器访问异常。

公开(公告)号：US20160179379A1

公开(公告)日：2016-06-23

申请号：US14977699

申请日：2015-12-22

Applicant: Teradata US, Inc.

Inventor： Daniel D. Hoffman ,  William T. Sanders ,  Supen B. Shah ,  David E. Steinke

IPC: G06F3/06 ,  G06F12/06

CPC classification number: G06F3/061 ,  G06F3/0631 ,  G06F3/0655 ,  G06F3/0685 ,  G06F3/0688 ,  G06F12/0638 ,  G06F12/08 ,  G06F2212/1016 ,  G06F2212/205 ,  G06F2212/217 ,  G06F2212/261 ,  G06F2212/502

Abstract: A system and method for allocating different temperature data to storage devices within a computer system including inexpensive non-volatile storage, such as hard disk drive (HDD) storage devices; expensive non-volatile storage, such as solid-state drive (SSD) storage devices; and expensive volatile storage, such as system cache memory. The system and method allocates cold to warm data having access frequencies up to a first access frequency threshold to inexpensive non-volatile storage; allocates hot data having access frequencies greater than the first access frequency value and ranging up to a second access frequency threshold, to expensive non-volatile storage; and allocates very hot data having access frequencies greater than the second access frequency value and which resides during normal system operation in expensive volatile storage, to said inexpensive non-volatile storage.

Abstract translation: 一种用于将不同温度数据分配到包括诸如硬盘驱动器（HDD）存储设备的廉价非易失性存储器的计算机系统内的存储设备的系统和方法; 昂贵的非易失性存储，如固态硬盘（SSD）存储设备; 和昂贵的易失性存储，如系统缓存存储器。 该系统和方法将具有高达第一接入频率阈值的接入频率的冷数据分配给廉价的非易失性存储; 将具有大于第一访问频率值的访问频率和范围高达第二访问频率阈值的热数据分配到昂贵的非易失性存储器; 并且将具有大于第二访问频率值的访问频率的非常热的数据分配给昂贵的易失性存储器中的正常系统操作期间的非常热的数据。

公开(公告)号：US09354885B1

公开(公告)日：2016-05-31

申请号：US14990984

申请日：2016-01-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael K. Gschwind ,  Valentina Salapura

IPC: G06F9/38

CPC classification number: G06F9/3808 ,  G06F9/30058 ,  G06F9/30145 ,  G06F9/3802 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/452 ,  G06F2212/502

Abstract: Processing of an instruction fetch from an instruction cache is provided, which includes: determining whether the next instruction fetch is in a same cache line of the instruction cache as a last instruction fetch; and based, at least in part, on determining that the next instruction fetch is in the same cache line, suppressing for the next instruction fetch one or more instruction cache-related directory accesses, and forcing for the next instruction an address match signal for the same cache line. The suppressing may include generating a known-to-hit signal where the next fetch is in the same cache line, and the last fetch is not a branch instruction, and issuing an instruction cache hit where a cache line segment of the same cache line having the next instruction has a valid validity bit, the valid validity bit having been retrieved and maintained based on a most-recent, instruction cache-directory-accessed fetch.

Abstract translation: 提供从指令高速缓冲存储器提取指令的处理，其包括：确定下一个指令提取是否在与指令高速缓存相同的高速缓存行中，作为最后指令提取; 并且至少部分地基于确定下一个指令提取在相同的高速缓存行中，抑制下一个指令获取一个或多个与指令高速缓存相关的目录访问，并强制下一个指令，以便为 相同的缓存行。 抑制可以包括生成已知的命中信号，其中下一个提取位于相同的高速缓存行中，并且最后一次获取不是分支指令，并且发出指令高速缓存命中，其中相同高速缓存行的高速缓存行段具有 下一条指令具有有效的有效位，基于最新的指令缓存目录访问的提取已经检索和维护了有效的有效位。

公开(公告)号：US20160140046A1

公开(公告)日：2016-05-19

申请号：US14540585

申请日：2014-11-13

Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD.

Inventor： Colin Eddy

IPC: G06F12/10 ,  G06F12/02

CPC classification number: G06F12/1009 ,  G06F12/0215 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2212/1021 ,  G06F2212/152 ,  G06F2212/502 ,  G06F2212/654

Abstract: A hardware prefetch tablewalk system for a microprocessor including a tablewalk engine that is configured to perform hardware prefetch tablewalk operations without blocking software-based tablewalk operations. Tablewalk requests include a priority value, in which the tablewalk engine is configured to compare priorities of requests in which a higher priority request may terminate a current tablewalk operation. Hardware prefetch tablewalk requests having the lowest possible priority so that they do not bump higher priority tablewalk operations and are bumped by higher priority tablewalk requests. The priority values may be in the form of age values indicative of relative ages of operations being performed. The microprocessor may include a hardware prefetch engine that performs boundless hardware prefetch pattern detection that is not limited by page boundaries to provide the hardware prefetch tablewalk requests.

Abstract translation: 一种用于微处理器的硬件预取行进台系统，包括配置为执行硬件预取行进操作而不阻止基于软件的行走操作的行进台引擎。 行进路径请求包括一个优先级值，其中桌面引擎被配置为比较优先级高的请求可以终止当前行进步骤操作的请求的优先级。 硬件预取行进请求具有最低可能的优先级，以便它们不会碰到更高优先级的行进操作，并被更高优先级的行进请求所冲撞。 优先级值可以是指示正在执行的操作的相对年龄的年龄值的形式。 微处理器可以包括执行无限硬件预取模式检测的硬件预取引擎，其不受页边界限制，以提供硬件预取行进请求。

公开(公告)号：US20160098353A1

公开(公告)日：2016-04-07

申请号：US14877523

申请日：2015-10-07

Applicant: GOOGLE INC.

Inventor： Shinye SHIU

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/1009 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0638 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0673 ,  G06F3/0683 ,  G06F12/0802 ,  G06F12/0864 ,  G06F12/0891 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/12 ,  G06F12/121 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/604 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  Y02D10/13 ,  Y02D10/22

Abstract: Provided are methods and systems for de-duplicating cache lines in physical memory by detecting cache line data patterns and building a link-list between multiple physical addresses and their common data value. In this manner, the methods and systems are applied to achieve de-duplication of an on-chip cache. A cache line filter includes one table that defines the most commonly duplicated content patterns and a second table that saves pattern numbers from the first table and the physical address for she duplicated cache line. Since a cache line duplicate can be detected during a write operation, each write can involve table lookup and comparison. If there is a hit in the table, only the address is saved instead of the entire data string.

Abstract translation: 提供了通过检测高速缓存线数据模式并在多个物理地址与其公共数据值之间建立链路列表来在物理存储器中去重复高速缓存行的方法和系统。 以这种方式，应用方法和系统来实现片上高速缓存的重复数据删除。 高速缓存行过滤器包括一个定义最常复制的内容模式的表以及从第一个表中保存模式编号的第二个表以及重复的高速缓存行的物理地址。 由于在写入操作期间可以检测到缓存行副本，所以每个写入可以涉及表查找和比较。 如果表中有命中，则只保存地址而不是整个数据字符串。

公开(公告)号：US09092486B2

公开(公告)日：2015-07-28

申请号：US14146565

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrew G. Kegel

IPC: G06F11/30

CPC classification number: G06F11/3051 ,  G06F11/3034 ,  G06F11/3065 ,  G06F11/3442 ,  G06F11/3476 ,  G06F12/02 ,  G06F12/0223 ,  G06F12/1081 ,  G06F17/40 ,  G06F2201/81 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/502

Abstract: A method of managing peripherals is performed in a device coupled to a processor in a computer system. In the method, information associated with I/O activity for one or more peripherals is recorded in a first segment of a log. A second segment of the log is identified based on a next-segment pointer associated with the first segment of the log. In response to detecting a lack of available capacity in the first segment of the log, information associated with further I/O activity for the one or more peripherals is recorded in the second segment of the log.

Abstract translation: 在耦合到计算机系统中的处理器的设备中执行管理外围设备的方法。 在该方法中，与一个或多个外围设备的I / O活动相关联的信息被记录在日志的第一段中。 基于与日志的第一段相关联的下一段指针来识别日志的第二段。 响应于检测到日志的第一段中的可用容量的缺乏，与一个或多个外围设备的进一步I / O活动相关联的信息被记录在日志的第二段中。

公开(公告)号：US20150149746A1

公开(公告)日：2015-05-28

申请号：US14536763

申请日：2014-11-10

Applicant: FUJITSU LIMITED

Inventor： Makoto SUGA ,  AKIO TOKOYODA ,  Koji HOSOE ,  Masatoshi Aihara ,  Yuta Toyoda

IPC: G06F9/30

CPC classification number: G06F12/00 ,  G06F9/30043 ,  G06F9/3824 ,  G06F12/023 ,  G06F13/00 ,  G06F2212/1024 ,  G06F2212/401 ,  G06F2212/502

Abstract: An arithmetic processing device promotes transmission efficiency between a processor and a memory. The arithmetic processing device has an arithmetic processing unit which issues an instruction accompanying with data which is sent to the memory, a judgment unit which judges whether or not a redundancy degree of the data which is accompanied with the instruction is more than a predetermined value, a compression unit which judges whether or not compress the data based on an waiting time and a compression time when the redundancy degree of the data is more than the predetermined value, and compress the data when judging that performs the compression, and an instruction arbitration unit which transfers the instruction accompanying with the compressed data to the memory when the compression unit performs the compression and transfers the instruction accompanying with the non-compressed data to the memory when the compression unit does not perform the compression.

Abstract translation: 算术处理装置提高处理器和存储器之间的传输效率。 算术处理装置具有运算处理单元，该运算处理单元发出伴随着发送给存储器的数据的指令，判断单元判断伴随该指令的数据的冗余度是否大于预定值， 压缩单元，其基于当数据的冗余度大于预定值时的等待时间和压缩时间来判断是否压缩数据，并且在执行压缩的判定时压缩数据;以及指令仲裁单元 当压缩单元执行压缩时，将压缩数据附带的指令传送到存储器，并且当压缩单元不执行压缩时，将伴随非压缩数据的指令传送到存储器。