公开(公告)号：US20230309229A1

公开(公告)日：2023-09-28

申请号：US18073670

申请日：2022-12-02

Applicant: TDK CORPORATION

Inventor： Takeshi OOHASHI ,  Yukio MITAKE ,  Daiki KUSUNOKI

IPC: H05K1/16 ,  H05K1/11

CPC classification number: H05K1/165 ,  H05K1/162 ,  H05K1/111 ,  H05K2201/09545 ,  H05K2201/10522 ,  H05K2201/10931 ,  H05K2201/10818

Abstract: An electronic component includes an insulator and an inductor pattern and a capacitor pattern which are arranged in the insulator. The inductor pattern and the capacitor pattern are electrically connected between one end and the other end of the first inductor pattern.

公开(公告)号：US20230163050A1

公开(公告)日：2023-05-25

申请号：US18152733

申请日：2023-01-10

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan Kalyani Koduri

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H05K1/18 ,  H01L23/552 ,  H05K3/34

CPC classification number: H01L23/49558 ,  H01L23/3135 ,  H01L23/49555 ,  H01L21/56 ,  H05K1/181 ,  H01L23/552 ,  H05K3/3426 ,  H05K2201/10931 ,  H01L23/49586 ,  H01L21/4842

Abstract: In examples, a semiconductor device comprises a semiconductor die, an opaque mold compound housing covering the semiconductor die, a conductive terminal extending from the mold compound housing, and an insulative coat covering the mold compound housing and at least a portion of the conductive terminal.

公开(公告)号：US09955579B2

公开(公告)日：2018-04-24

申请号：US15057518

申请日：2016-03-01

Applicant: Nitto Denko Corporation

Inventor： Hiroyuki Tanabe ,  Daisuke Yamauchi

IPC: H05K1/09 ,  H05K1/11 ,  H05K3/18 ,  H05K3/40 ,  H05K1/02 ,  H05K3/38 ,  G11B5/48 ,  H05K3/00 ,  H05K3/28

CPC classification number: H05K1/11 ,  G11B5/484 ,  H05K1/0242 ,  H05K1/09 ,  H05K1/111 ,  H05K3/0061 ,  H05K3/181 ,  H05K3/285 ,  H05K3/384 ,  H05K3/40 ,  H05K2201/0154 ,  H05K2201/09081 ,  H05K2201/10931 ,  H05K2203/072

Abstract: A printed circuit board includes first and second insulating layers, a wiring trace, a metal thin film, and a connection terminal. The wiring trace is formed on the first insulating layer. The metal thin film is formed on the wiring trace, and has a thickness larger than 0 nm and not more than 150 nm. The second insulating layer is formed on the first insulating layer to cover the metal thin film. The connection terminal is formed on the first insulating layer to be electrically connected to the wiring trace and exposed from the second insulating layer.

公开(公告)号：US09577304B2

公开(公告)日：2017-02-21

申请号：US14637898

申请日：2015-03-04

Applicant: ADVANCED FLEXIBLE CIRCUITS CO., LTD.

Inventor： Chih-Heng Chuo ,  Gwun-Jin Lin ,  Kuo-Fu Su

IPC: H03H7/38 ,  H01P1/22 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/34

CPC classification number: H01P1/227 ,  H03H7/38 ,  H05K1/0225 ,  H05K1/0251 ,  H05K1/116 ,  H05K1/189 ,  H05K3/3447 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09718 ,  H05K2201/10931

Abstract: Disclosed is an attenuation reduction structure for high-frequency connection pads of a circuit board with an insertion component. The circuit board includes at least one pair of differential mode signal lines formed thereon. A substrate has upper and lower surfaces respectively provided with at least one pair of upper connection pads and lower connection pads. A first metal layer is formed on the lower surface of the substrate. The first metal layer includes an attenuation reduction grounding pattern structure. The attenuation reduction grounding pattern structure includes a hollow area and at least one protruded portion. The protruded portion extends from the first metal layer in a direction toward the lower connection pads.

Abstract translation: 公开了一种具有插入部件的电路板的高频连接焊盘的衰减减小结构。 电路板包括形成在其上的至少一对差模信号线。 衬底具有分别设置有至少一对上连接焊盘和下连接焊盘的上表面和下表面。 第一金属层形成在基板的下表面上。 第一金属层包括衰减减小接地图案结构。 衰减降低接地图案结构包括中空区域和至少一个突出部分。 突出部分沿着朝向下连接焊盘的方向从第一金属层延伸。

公开(公告)号：US20160262265A1

公开(公告)日：2016-09-08

申请号：US15057518

申请日：2016-03-01

Applicant: Nitto Denko Corporation

Inventor： Hiroyuki TANABE ,  Daisuke YAMAUCHI

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/18 ,  H05K1/09

CPC classification number: H05K1/11 ,  G11B5/484 ,  H05K1/0242 ,  H05K1/09 ,  H05K1/111 ,  H05K3/0061 ,  H05K3/181 ,  H05K3/285 ,  H05K3/384 ,  H05K3/40 ,  H05K2201/0154 ,  H05K2201/09081 ,  H05K2201/10931 ,  H05K2203/072

Abstract: A printed circuit board includes first and second insulating layers, a wiring trace, a metal thin film, and a connection terminal. The wiring trace is formed on the first insulating layer. The metal thin film is formed on the wiring trace, and has a thickness larger than 0 nm and not more than 150 nm. The second insulating layer is formed on the first insulating layer to cover the metal thin film. The connection terminal is formed on the first insulating layer to be electrically connected to the wiring trace and exposed from the second insulating layer.

Abstract translation: 印刷电路板包括第一和第二绝缘层，布线迹线，金属薄膜和连接端子。 布线迹线形成在第一绝缘层上。 金属薄膜形成在布线轨迹上，其厚度大于0nm且不大于150nm。 第二绝缘层形成在第一绝缘层上以覆盖金属薄膜。 连接端子形成在第一绝缘层上以与布线迹线电连接并从第二绝缘层暴露。

公开(公告)号：US07378743B2

公开(公告)日：2008-05-27

申请号：US11453163

申请日：2006-06-13

Applicant: Sheng-Yuan Lee

Inventor： Sheng-Yuan Lee

IPC: H01L23/48

CPC classification number: H01L23/3107 ,  H01L23/49541 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0243 ,  H05K3/341 ,  H05K3/3421 ,  H05K3/3442 ,  H05K2201/0792 ,  H05K2201/10689 ,  H05K2201/10727 ,  H05K2201/10931 ,  H05K2201/10969 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A circuit board suitable for being electrically connected to a chip package is provided. The chip package has a chip pad and a plurality of inner leads. The circuit board includes at least one patterned conductive layer and at least one insulating layer. The patterned conductive layer has at least one first pad and at least one second pad. The first pad has an extension part and is suitable for being electrically connected to the chip pad. The second pad is suitable for being electrically connected to one end of at least one of the inner leads, while the other end of the inner lead suitable for being electrically connected to the second pad has a projection at least partially overlapping the extension part on the patterned conductive layer. Moreover, the patterned conductive layer is disposed outside the insulating layer.

Abstract translation: 提供了适于电连接到芯片封装的电路板。 芯片封装具有芯片焊盘和多个内部引线。 电路板包括至少一个图案化导电层和至少一个绝缘层。 图案化导电层具有至少一个第一焊盘和至少一个第二焊盘。 第一焊盘具有延伸部分，并且适于电连接到芯片焊盘。 第二垫适于电连接到至少一个内引线的一端，而内引线的另一端适于与第二焊盘电连接，其突出部分至少部分地与第二焊盘上的延伸部分重叠 图案化导电层。 此外，图案化导电层设置在绝缘层的外部。

公开(公告)号：US20050189627A1

公开(公告)日：2005-09-01

申请号：US11065108

申请日：2005-02-25

Applicant: Fujio Ito ,  Hiromichi Suzuki ,  Takashi Miwa ,  Tokuji Toida

Inventor： Fujio Ito ,  Hiromichi Suzuki ,  Takashi Miwa ,  Tokuji Toida

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/60 ,  H01L23/12 ,  H01L23/31 ,  H01L23/495 ,  H01L23/50 ,  H05K1/18 ,  H05K3/34

CPC classification number: H01L23/3107 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K3/3426 ,  H05K3/3442 ,  H05K2201/09709 ,  H05K2201/10689 ,  H05K2201/10931 ,  H05K2201/10984 ,  Y02P70/613 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A surface mounting method for mounting semiconductor devices suppresses solder peeling defects which tried to occur during mounting. The method used for mounting semiconductor devices includes a process for preparing the semiconductor devices by obtaining multiple terminals by exposing a section of each of multiple leads protruding from a rear side of the plastic casing, and forming a layer of solder by solidifying a molten solder material; a process for supplying a solder paste material to multiple electrodes on a printed circuit board; and a process for melting the solder paste of the multiple electrodes and connecting each of the multiple terminals with the multiple electrodes.

Abstract translation: 用于安装半导体器件的表面安装方法抑制了在安装期间发生的焊料剥离缺陷。 用于安装半导体器件的方法包括通过从塑料外壳的后侧突出的多个引线的一部分暴露出多个端子来制备半导体器件的工艺，以及通过使熔融焊料材料固化形成一层焊料 ; 用于将焊膏材料供应到印刷电路板上的多个电极的工艺; 以及用于熔化多个电极的焊膏并将多个端子中的每一个与多个电极连接的工艺。

公开(公告)号：US20050012187A1

公开(公告)日：2005-01-20

申请号：US10892483

申请日：2004-07-16

Applicant: Koujiro Kameyama ,  Kiyoshi Mita

Inventor： Koujiro Kameyama ,  Kiyoshi Mita

IPC: H01L23/12 ,  H01L21/68 ,  H01L23/31 ,  H01L23/48 ,  H01L23/495 ,  H05K3/34 ,  H01L21/48 ,  H01L31/11

CPC classification number: H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2221/68331 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/181 ,  H05K3/3426 ,  H05K3/3442 ,  H05K2201/09154 ,  H05K2201/10772 ,  H05K2201/10931 ,  Y02P70/613 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device comprises a semiconductor element and electrodes electrically connected to the semiconductor element, the semiconductor element and the electrodes being sealed by a sealing agent having an insulating property, the electrodes being exposed around a mounting surface that is joined via a joining agent to an external mounting circuit board, wherein the electrodes are shaped so that the joining agent is visually identifiable from side surfaces surrounding the mounting surface when the mounting surface is joined via the joining agent to the mounting circuit board.

Abstract translation: 半导体器件包括半导体元件和电连接到半导体元件的电极，半导体元件和电极被具有绝缘性能的密封剂密封，电极暴露在通过接合剂连接到安装表面上 外部安装电路板，其中电极被成形为使得当安装表面经由接合剂连接到安装电路板时，接合剂可以从围绕安装表面的侧表面可视地识别。

公开(公告)号：US06200829B1

公开(公告)日：2001-03-13

申请号：US09299158

申请日：1999-04-22

Applicant: Dennis Brian Miller ,  Grace M. O'Malley ,  Brian R. Kemper

Inventor： Dennis Brian Miller ,  Grace M. O'Malley ,  Brian R. Kemper

IPC: H01L2144

CPC classification number: H01L24/80 ,  G06K19/07745 ,  G06K19/0775 ,  H01L23/49855 ,  H01L2224/48091 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/183 ,  H05K3/28 ,  H05K3/321 ,  H05K3/3426 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/10477 ,  H05K2201/10689 ,  H05K2201/10931 ,  H01L2924/00014

Abstract: A microelectronic assembly (10), such as a smart card, is formed by attaching a component subassembly (34) to a substrate (12). The substrate (12) includes a face (26) and defines a via (28) having a via opening (30) at the face (26). The substrate (12) further defines a component cavity (32) at the face (26) that is spaced apart from the via (28). An electrical element (14), such as a wound antenna, is disposed within the substrate (12) and includes a terminal (24) at the via (28). The component subassembly (34) is formed by mounting an integrated circuit component (16) onto a metallic lead (18). The integrated circuit component (16) is electrically connected to the metallic lead (18) by a wire lead (36). A protuberance (20) is connected to the metallic lead (18), preferably by forming a loop from a wire bond. A polymeric body (56) is formed about the component (16) and wire leads (36). The component subassembly (34) is superposed onto the substrate (12), and the component (16) is received in the component cavity (32). The metallic lead (18) is affixed to the face (26) and overlies the via opening (30). The protuberance (20) extends into the via (28) and contacts a conductive body (22) within the via (28). The conductive body (22) electrically connects the protuberance (20) and the terminal (24).

Abstract translation: 诸如智能卡的微电子组件（10）通过将部件子组件（34）附接到基板（12）而形成。 衬底（12）包括面（26）并且限定了在面（26）处具有通孔开口（30）的通孔（28）。 基板（12）还在与通孔（28）间隔开的面（26）处限定一个部件空腔（32）。 诸如伤口天线的电气元件（14）设置在衬底（12）内，并且在通孔（28）处包括端子（24）。 组件子组件（34）通过将集成电路部件（16）安装到金属引线（18）上而形成。 集成电路部件（16）通过引线（36）与金属引线（18）电连接。 突起（20）连接到金属引线（18），优选地通过从引线接合形成环。 围绕组件（16）和导线（36）形成聚合体（56）。 组件子组件（34）重叠在基板（12）上，并且部件（16）被容纳在部件空腔（32）中。 金属引线（18）固定在面（26）上并覆盖通孔（30）。 突起（20）延伸到通孔（28）中并与通孔（28）内的导电体（22）接触。 导电体（22）电连接突起（20）和端子（24）。

公开(公告)号：US5109269A

公开(公告)日：1992-04-28

申请号：US726780

申请日：1991-07-08

Applicant: Ofer Holzman

Inventor： Ofer Holzman

IPC: H05K3/34 ,  H05K3/40 ,  H05K13/04

CPC classification number: H05K3/341 ,  H05K13/046 ,  H05K3/3426 ,  H05K2201/09663 ,  H05K2201/09781 ,  H05K2201/1028 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2201/10931 ,  H05K2201/10962 ,  H05K2201/10969 ,  H05K2203/048 ,  H05K3/4015 ,  Y02P70/613 ,  Y10S269/903 ,  Y10T29/49144

Abstract: An SMT electronic component is mounted to a solder-bearing floatation plate by fusible or other heat-responsive releasable mounting means which suspend the component above the floatation plate. The bottom of the floatation plate is effectively substantially the mirror image of a component-positioning pad formed on the board surface adjacent the solder-bearing contact pads corresponding to the electrical contacts on the component. In the assembly process, the floatation plate is placed on the positioning pad. The solder on the bottom of the floatation plate has a melting point lower than the release temperature of the mounting means and the melting point of the solder on the contact pads. With the floatation plate on the component-positioning pad, on heating the solder on the floatation plate liquifies first, wetting the component-positioning pad and floating the floatation plate and component on a thin film of molten solder. Surface tension forces bring the floatation plate into registry with the component-positioning pad. On further heating, the solder on the contact pads liquifies, and the heat-responsive mounting means allows the component to fall freely onto the contact pads. Guide means are provided to prevent rotational and lateral displacement of the component during the fall. The disclosure includes alternative floatation plate constructions and component mounting arrangements.

Abstract translation: SMT电子部件通过可熔或其它热响应的可释放的安装装置安装到焊料浮动板上，该安装装置将浮动板上方的部件悬挂。 漂浮板的底部基本上是形成在板表面上的与形成在组件上的电触点对应的焊料支承接触垫相邻的部件定位焊盘的镜像。 在组装过程中，将浮选板放置在定位垫上。 浮选板底部的焊料的熔点低于安装装置的释放温度和接触焊盘上焊料的熔点。 通过浮动板在组件定位垫上，加热漂浮板上的焊料首先液化，润湿组件定位垫，并将浮选板和组件浮在熔融焊料薄膜上。 表面张力使浮板与元件定位垫对准。 在进一步加热时，接触焊盘上的焊料液化，并且热响应安装装置允许部件自由落入接触焊盘。 提供引导装置以防止部件在坠落期间的旋转和横向位移。 本公开包括替代的漂浮板结构和部件安装布置。