公开(公告)号：US10173464B2

公开(公告)日：2019-01-08

申请号：US15582778

申请日：2017-05-01

Applicant: Or-Ment LLC

Inventor： Zvi Or-Bach

IPC: B60B19/00 ,  B60L15/20 ,  B60C11/04 ,  B62D11/04

Abstract: An electrical family car, including: an electrically driven motor; and wheels with a radius larger than 90 cm. In such cars one of the dominating energy losses is directly related to the car axial to wheel friction. The car efficiency could therefore be increased by increasing the car wheel diameter which could yield a larger traveling distance for the same axial to wheel friction related energy loss.

公开(公告)号：US20190006192A1

公开(公告)日：2019-01-03

申请号：US16114211

申请日：2018-08-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L21/48 ,  H01L23/34 ,  H01L23/498 ,  H01L27/098 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L25/065 ,  H01L27/092 ,  H01L23/60 ,  H01L23/522

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a plurality of fourth transistors overlaying, at least in part the third transistors; a second metal layer overlaying, at least in part the fourth transistors; where the fourth transistors are aligned with less than 100 nm misalignment to the first transistors, where at least one of the plurality of vias has a radius of less than 200 nm, where a memory cell includes at least one of the third transistors.

公开(公告)号：US20180350689A1

公开(公告)日：2018-12-06

申请号：US16101478

申请日：2018-08-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/822 ,  H03K19/177 ,  H03K19/0948 ,  H03K17/687 ,  H01L29/786 ,  H01L29/78 ,  H01L27/118 ,  H01L27/112 ,  H01L27/11 ,  H01L27/108 ,  H01L27/105 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02 ,  H01L25/18 ,  H01L25/065 ,  H01L23/544 ,  H01L23/525 ,  H01L23/36 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/683 ,  G11C29/00 ,  G11C17/14 ,  G11C17/06 ,  G11C16/04 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L21/8221 ,  G11C5/025 ,  G11C5/063 ,  G11C16/0483 ,  G11C29/82 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/845 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/544 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/785 ,  H01L29/78696 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/207 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K19/0948 ,  H03K19/17704 ,  H03K19/17756 ,  H03K19/17764 ,  H03K19/17796

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one metal layer interconnecting the first transistors and forming a plurality of logic gates; a first intermediate metal layer overlaying the at least one metal layer; a second intermediate metal layer overlaying the first intermediate metal layer; where the first intermediate metal layer has a first current carrying capacity, where the second intermediate metal layer has a second current carrying capacity, and where the first current carrying capacity is significantly greater than the second current carrying capacity; a plurality of second transistors overlaying the second intermediate metal layer; and a top metal layer overlaying the second transistors; and a memory cell, where at least one of the second transistors includes a polysilicon transistor channel, where the second transistors are precisely aligned to the first transistors.

公开(公告)号：US10127344B2

公开(公告)日：2018-11-13

申请号：US14672202

申请日：2015-03-29

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: G06F17/50

Abstract: A method of designing a 3D Integrated Circuit, the method including: performing partitioning to at least a first strata and a second strata; then performing a first placement of the first strata using a 2D placer executed by a computer, where the 2D placer is a Computer Aided Design (CAD) tool currently used in the industry for two-dimensional devices; and performing a second placement of the second strata based on the first placement, where the partitioning includes a partition between logic and memory, and where the logic includes at least one decoder representation for the memory.

公开(公告)号：US20180294343A1

公开(公告)日：2018-10-11

申请号：US16004404

申请日：2018-06-10

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L29/66 ,  H01L23/50 ,  H01L23/48 ,  H01L23/34 ,  H01L27/088

Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors, contacts, and a first metal layer, where a portion of the first single crystal transistors are interconnected, where the interconnected includes the first metal layer and the contacts, and where the portion of the first single crystal transistors are interconnected forms memory control circuits; a second level overlaying the first level, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; a fourth level overlaying the third level, the fourth level including a plurality of fourth transistors; and a second metal layer overlaying the fourth level, where the plurality of second transistors are aligned to the plurality of first transistors with a less than 40 nm alignment error.

公开(公告)号：US20180204835A1

公开(公告)日：2018-07-19

申请号：US15922913

申请日：2018-03-16

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Zeev Wurman

IPC: H01L27/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/45 ,  H01L29/423 ,  H01L27/12 ,  H01L27/118 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/112 ,  H01L27/11 ,  H01L27/108 ,  H01L27/105 ,  H01L27/088 ,  H01L27/02 ,  H01L23/544 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L23/367 ,  H01L21/84 ,  H01L21/822 ,  H01L21/762 ,  G03F9/00 ,  H01L21/268 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L27/0688 ,  B82Y10/00 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/268 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/84 ,  H01L23/367 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66272 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66901 ,  H01L29/775 ,  H01L29/78639 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/78696 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/80001 ,  H01L2924/00 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025

Abstract: A semiconductor device including: a first layer including a first memory cell, the first memory cell including a first transistor; a second layer including a second memory cell, the second memory cell including a second transistor; a periphery layer including a memory peripherals transistor, the periphery layer is disposed underneath the first layer; a memory including at least the first memory cell and the second memory cell, where the second memory cell overlays the first memory cell, where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where a peripherals circuit includes the memory peripherals transistor and controls the memory; a first external connections underlying the periphery layer, the first external connections includes connections from the device to a first external device; and a second external connections overlying the second layer, the second external connections includes connections from the device to a second external device.

公开(公告)号：US20180197812A1

公开(公告)日：2018-07-12

申请号：US15913917

申请日：2018-03-06

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L23/498 ,  H01L23/34 ,  H01L27/098 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L25/065 ,  H01L23/60 ,  H01L23/522

CPC classification number: H01L23/49827 ,  H01L21/823487 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3732 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/098 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; a plurality of third transistors overlaying the second transistors; a second metal layer overlaying the third transistors; and Input/Output pads to provide connection to external devices, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes an Electrostatic Discharge (“ESD”) structure connected to at least one of the Input/Output pads, where at least one of the third transistors is a junction-less transistor, and where a memory cell includes at least one of the third transistors.

公开(公告)号：US10014292B2

公开(公告)日：2018-07-03

申请号：US15477106

申请日：2017-04-02

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L23/02 ,  H01L27/06 ,  H01L25/07 ,  H01L25/11 ,  H01L21/683 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L27/0688 ,  H01L21/6835 ,  H01L23/544 ,  H01L25/071 ,  H01L25/117 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L2221/68368 ,  H01L2223/54426 ,  H01L2224/18

Abstract: A 3D semiconductor device, the device including: a first die including a first transistors layer and a first interconnection layer; and a second die overlaying the first die, the second die including a second transistors layer and a second interconnection layer, where the second die thickness is less than 2 microns, and where the first die is substantially larger than the second die.

公开(公告)号：US09941332B2

公开(公告)日：2018-04-10

申请号：US15409740

申请日：2017-01-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Zeev Wurman

IPC: H01L27/10 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00 ,  H01L29/04 ,  H01L29/167 ,  H01L29/78 ,  H01L29/66 ,  H01L27/105 ,  H01L21/02 ,  H01L21/324 ,  H01L21/223 ,  H01L21/311

CPC classification number: H01L27/2436 ,  G11C13/0021 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/2236 ,  H01L21/31116 ,  H01L21/324 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/249 ,  H01L29/04 ,  H01L29/167 ,  H01L29/66568 ,  H01L29/78 ,  H01L29/78696 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1616 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/00011 ,  H01L2224/80001

Abstract: A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor overlaying the second transistor or underneath the first transistor, where the second memory cell overlays the first memory cell, and where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.

公开(公告)号：US09911627B1

公开(公告)日：2018-03-06

申请号：US13864244

申请日：2013-04-17

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L21/00 ,  H01L21/48

CPC classification number: H01L21/4871 ,  H01L21/823487 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3732 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/098 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for processing a 3D semiconductor device, the method including: processing a first layer comprising first transistors, forming a first power distribution grid to provide power to the first transistors, processing a second layer overlying the first transistors and including second transistors, where the second layer includes a through layer via with diameter of less than 150 nm, forming a second power distribution grid overlaying the second transistors, where the first power distribution grid includes first power conductors and the second power distribution grid includes second power conductors, and where the second power conductors are substantially wider or thicker than the first power conductors, and where the device includes a plurality of vias to connect the second power distribution grid to the first power distribution grid.