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    Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch
    51.
    发明授权
    Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch 有权
    在具有大晶格失配的衬底上形成松散半导体缓冲层的方法

    公开(公告)号：US07166522B2

    公开(公告)日：2007-01-23

    申请号：US10865433

    申请日：2004-06-10

    申请人： Jin Ping Liu ,  Dong Kyun Sohn ,  Liang Choo Hsia

    发明人： Jin Ping Liu ,  Dong Kyun Sohn ,  Liang Choo Hsia

    IPC分类号： H01L21/20

    CPC分类号： C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/0262 ,  H01L29/1054

    摘要： A method of forming a relaxed silicon-germanium layer for use as an underlying layer for a subsequent, overlying tensile strain silicon layer, has been developed. The method features initial growth of a underlying first silicon-germanium layer on a semiconductor substrate, compositionally graded to feature the largest germanium content at the interface of the first silicon-germanium layer and the semiconductor substrate, with the level of germanium decreasing as the growth of the graded first silicon-germanium layer progresses. This growth sequence allows the largest lattice mismatch and greatest level of threading dislocations to be present at the bottom of the graded silicon-germanium layer, with the magnitude of lattice mismatch and threading dislocations decreasing as the growth of the graded silicon-germanium layer progresses. In situ growth of an overlying silicon-germanium layer featuring uniform or non-graded germanium content, results in a relaxed silicon-germanium layer with a minimum of dislocations propagating from the underlying graded silicon-germanium layer. In situ growth of a silicon layer results in a tensile strain, low defect density layer to be used for MOSFET device applications.

    摘要翻译： 已经开发了形成用于随后的上覆拉伸应变硅层的下层的松弛硅锗层的方法。 该方法的特征在于半导体衬底上的底层第一硅 - 锗层的初始生长，其组成分级以在第一硅 - 锗层和半导体衬底的界面处具有最大的锗含量，锗的含量随着生长 的分级第一硅锗层进行。 该生长序列允许最大的晶格失配和最高级别的穿透位错存在于渐变硅 - 锗层的底部，随着梯度硅 - 锗层的生长进行，晶格失配和穿透位错的大小减小。 具有均匀或非分级锗含量的上覆硅锗层的原位生长导致松弛的硅 - 锗层，其中最小的位错从下面的梯度硅 - 锗层传播。 硅层的原位生长导致用于MOSFET器件应用的拉伸应变，低缺陷密度层。

    Method of forming wing gate transistor for integrated circuits
    52.
    发明授权
    Method of forming wing gate transistor for integrated circuits 失效
    形成用于集成电路的翼栅晶体管的方法

    公开(公告)号：US07056799B2

    公开(公告)日：2006-06-06

    申请号：US10820664

    申请日：2004-04-07

    申请人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

    发明人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

    IPC分类号： H01L21/336 ,  H01L21/425

    CPC分类号： H01L29/6653 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.

    摘要翻译： 提供一种用于形成半导体器件的系统。 在半导体衬底上形成栅介电材料层，栅极材料层和盖材料层。 盖材料和栅极材料的一部分被加工以形成盖和门体部分。 门体部分上的翼部由栅极材料的剩余部分形成。 栅极主体部分的翼部的下方的栅介质材料被去除以形成栅极电介质。 使用门主体部分和机翼，在半导体衬底中形成轻掺杂的源极/漏极区域。

    Use of amorphous carbon as a removable ARC material for dual damascene fabrication
    53.
    发明授权
    Use of amorphous carbon as a removable ARC material for dual damascene fabrication 失效
    使用无定形碳作为可拆卸的ARC材料进行双镶嵌制造

    公开(公告)号：US06787452B2

    公开(公告)日：2004-09-07

    申请号：US10290629

    申请日：2002-11-08

    申请人： John Sudijono ,  Liang Choo Hsia ,  Liu Huang

    发明人： John Sudijono ,  Liang Choo Hsia ,  Liu Huang

    IPC分类号： H01L214763

    CPC分类号： H01L21/76808 ,  H01L21/0276 ,  H01L21/31144 ,  H01L21/3146 ,  H01L21/76802 ,  Y10S438/952

    摘要： An improved method of controlling a critical dimension during a photoresist patterning process is provided which can be applied to forming vias and trenches in a dual damascene structure. An amorphous carbon ARC is deposited on a substrate by a PECVD method. Preferred conditions are a RF power from 50 to 500 Watts, a bias of 500 to 2000 Watts, a chamber and substrate temperature of 300° C. to 400° C. with a trimethylsilane flow rate of 50 to 200 sccm, a helium flow rate of 100 to 1000 sccm, and an argon flow rate of 50 to 200 sccm. Argon plasma imparts an amorphous character to the film. The refractive index (n and k) can be tuned for a variety of photoresist applications including 193 nm, 248 nm, and 365 nm exposures. The &agr;-carbon layer provides a high etch selectivity relative to oxide and can be easily removed with a plasma etch.

    摘要翻译： 提供了一种在光致抗蚀剂图案化工艺期间控制临界尺寸的改进方法，其可以应用于在双镶嵌结构中形成通路和沟槽。 通过PECVD方法将非晶碳ARC沉积在衬底上。 优选的条件是50至500瓦的RF功率，500至2000瓦特的偏压，室和基板温度为300℃至400℃，三甲基硅烷流速为50至200sccm，氦流量 为100〜1000sccm，氩气流量为50〜200sccm。 氩等离子体为电影赋予无定形特征。 折射率（n和k）可以针对各种光刻胶应用进行调整，包括193 nm，248 nm和365 nm曝光。 α碳层相对于氧化物提供高蚀刻选择性，并且可以容易地用等离子体蚀刻去除。

    Floating body ESD protection circuit
    54.
    发明授权
    Floating body ESD protection circuit 有权
    浮体静电保护电路

    公开(公告)号：US06452235B1

    公开(公告)日：2002-09-17

    申请号：US09664108

    申请日：2000-09-19

    申请人： Liang-Choo Hsia

    发明人： Liang-Choo Hsia

    IPC分类号： H01L2362

    CPC分类号： H01L27/0266

    摘要： A floating body ESD protection circuit positioned between and coupled to an I/O pad and an internal circuit. A p-type depletion mode transistor is used to control the body of an n-type enhancement mode transistor. When the p-type depletion mode transistor is triggered, the body of n-type enhancement mode transistor remains grounded. If the p-type depletion mode transistor has not been triggered, the body remains in a floating state, lowering the range of the snapback voltage. As a consequence the ESD protection circuit is able to function more rapidly. Similarly, an n-type depletion mode transistor is used to control the body of a p-type enhancement mode transistor. When the n-type depletion mode transistor is triggered, the body remains coupled to a high voltage. If the n-type depletion mode transistor has not been triggered, the body is in a floating state. Thus, the range of the snapback voltage can be lowered, enabling the ESD protection circuit to function more rapidly.

    摘要翻译： 位于I / O焊盘和内部电路之间并耦合到I / O焊盘和内部电路之间的浮体ESD保护电路。 p型耗尽型晶体管用于控制n型增强型晶体管的主体。 当p型耗尽型晶体管被触发时，n型增强型晶体管的本体保持接地。 如果p型耗尽型晶体管未被触发，则主体保持在浮置状态，降低了快速恢复电压的范围。 因此，ESD保护电路能够更快地运行。 类似地，使用n型耗尽型晶体管来控制p型增强型晶体管的主体。 当n型耗尽型晶体管被触发时，主体保持耦合到高电压。 如果n型耗尽型晶体管未被触发，则主体处于浮动状态。 因此，可以降低回跳电压的范围，使得ESD保护电路能够更快地起作用。

    Circuit structure with an anti-reflective layer
    55.
    发明授权
    Circuit structure with an anti-reflective layer 失效
    具有抗反射层的电路结构

    公开(公告)号：US06043547A

    公开(公告)日：2000-03-28

    申请号：US870896

    申请日：1997-06-06

    申请人： Liang-Choo Hsia ,  Thomas Chang

    发明人： Liang-Choo Hsia ,  Thomas Chang

    IPC分类号： G03F1/00 ,  G03F7/09 ,  H01L21/027 ,  H01L31/0232 ,  H01L23/48 ,  H01L23/52 ,  H01L23/58

    CPC分类号： H01L21/0276 ,  G03F1/46 ,  G03F1/52 ,  G03F7/091 ,  Y10S430/151 ,  Y10S438/952

    摘要： An antireflection coating (116) for use in fabricating integrated circuits and electronic devices comprises a film of chromium oxide, CrO, or chromium suboxide, CrO.sub.x where x

    摘要翻译： 用于制造集成电路和电子器件的抗反射涂层（116）包括氧化铬，CrO或低氧化铬铬，其中x <1的CrO x。 当施加在高反射层（114）上时，抗反射层减少光致抗蚀剂层（118）中的驻波和地形凹陷。 高反射层可以是金属，例如铝或金，硅化物或半导体，例如硅。 这些涂层优选通过溅射室中的具有氧的分压的铬靶的反应溅射来制造。 抗反射层主要通过吸收而不是波形匹配原理起作用。 该抗反射层表现出良好的粘附性并且可以集成到该装置中。 将层集成到器件中可以减少下层中的应力并提高器件的产量和可靠性。

    Stacked capacitor having improved charge storage capacity
    56.
    发明授权
    Stacked capacitor having improved charge storage capacity 失效
    具有改进的电荷存储容量的堆叠电容器

    公开(公告)号：US6008515A

    公开(公告)日：1999-12-28

    申请号：US74486

    申请日：1998-05-06

    申请人： Liang-Choo Hsia ,  Thomas Chang

    发明人： Liang-Choo Hsia ,  Thomas Chang

    IPC分类号： H01L21/02 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94

    CPC分类号： H01L28/87 ,  H01L28/88

    摘要： A method of forming a capacitor that has improved charge storage capacity in a high density memory device that has shallow trench isolation regions and a capacitor produced by the method are provided. The method includes the step of forming an oxide spacer that consists of a plurality of oxide layers deposited by two alternating methods of thermal CVD and plasma CVD. After a contact hole is first etched by a plasma etching technique, the hole is again decoratively etched by an etchant such as hydrogen fluoride which has a high selectivity toward oxide layers formed by the plasma CVD method and a low selectivity toward oxide layers formed by the thermal CVD method. As a result, a corrugated side-wall of the contact hole is formed which affords the capacitor cell with an increased surface area leading to an improved charge storage capacity.

    摘要翻译： 提供一种形成在具有浅沟槽隔离区域的高密度存储器件中具有改进的电荷存储容量的电容器和通过该方法产生的电容器的方法。 该方法包括形成由通过热CVD和等离子体CVD两种交替方法沉积的多个氧化物层组成的氧化物间隔物的步骤。 在通过等离子体蚀刻技术首先蚀刻接触孔之后，通过诸如氟化氢的蚀刻剂再次装饰性地蚀刻孔，其对通过等离子体CVD法形成的氧化物层具有高选择性，并且对由 热CVD法。 结果，形成接触孔的波纹侧壁，其使电容器单元具有增加的表面积，从而提高电荷存储容量。

    Circuit structure which avoids latchup effect
    57.
    发明授权
    Circuit structure which avoids latchup effect 有权
    避免闭锁效应的电路结构

    公开(公告)号：US5990523A

    公开(公告)日：1999-11-23

    申请号：US306114

    申请日：1999-05-06

    申请人： Liang-Choo Hsia

    发明人： Liang-Choo Hsia

    IPC分类号： H01L27/092 ,  H01L29/76

    CPC分类号： H01L27/0921

    摘要： A circuit structure which avoids a latchup effect. An N-well is formed in a P-type substrate. An N-type contact is formed in the N-well. A PMOS is located on the N-well. A gate of the PMOS connects to an input terminal and a source region of the PMOS connects to a voltage source. A first NMOS and a second NMOS are located on the P-type substrate. A gate of the first NMOS connects to the input terminal, a source region of the first NMOS connects to a ground terminal, and a drain region of the first NMOS connects to an output terminal and a drain region of the PMOS. A gate of the second NMOS connects to the output terminal, a source region of the second NMOS connects to a voltage source, and a drain region of the second NMOS connects to the N-type contact.

    摘要翻译： 避免闭锁效应的电路结构。 在P型基板中形成N阱。 在N阱中形成N型接触。 PMOS位于N阱上。 PMOS的栅极连接到输入端子，PMOS的源极区域连接到电压源。 第一NMOS和第二NMOS位于P型衬底上。 第一NMOS的栅极连接到输入端子，第一NMOS的源极区域连接到接地端子，并且第一NMOS的漏极区域连接到PMOS的输出端子和漏极区域。 第二NMOS的栅极连接到输出端，第二NMOS的源极区连接到电压源，第二NMOS的漏极区连接到N型触点。

    Strained channel transistor structure and method
    60.
    发明授权
    Strained channel transistor structure and method 有权
    应变通道晶体管结构和方法

    公开(公告)号：US08754447B2

    公开(公告)日：2014-06-17

    申请号：US12857543

    申请日：2010-08-16

    申请人： Jin Ping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

    发明人： Jin Ping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/66636

    摘要： A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate.

    摘要翻译： 一种晶体管器件结构，包括：由第一材料形成的衬底部分; 以及源区域，漏极区域和形成在所述衬底中的沟道区域，所述源极和漏极区域包括与所述第一材料不同的多个第二材料岛，所述岛被布置成在所述沟道区域中引起应变 底物。