公开(公告)号：US20070034945A1

公开(公告)日：2007-02-15

申请号：US11586154

申请日：2006-10-24

申请人： Mark Bohr ,  Tahir Ghani ,  Stephen Cea ,  Kaizad Mistry ,  Christopher Auth ,  Mark Armstrong ,  Keith Zawadzki

发明人： Mark Bohr ,  Tahir Ghani ,  Stephen Cea ,  Kaizad Mistry ,  Christopher Auth ,  Mark Armstrong ,  Keith Zawadzki

IPC分类号： H01L29/76

CPC分类号： H01L29/66628 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848

摘要： Optimal strain in the channel region of a PMOS transistor is provided by silicon alloy material in the junction regions of the device in a non-planar relationship with the surface of the substrate. The silicon alloy material, the dimensions of the silicon alloy material, as well as the non-planar relationship of the silicon alloy material with the surface of the substrate are selected so that the difference between the lattice spacing of the silicon alloy material and of the substrate causes strains in the silicon alloy material below the substrate surface, as well as above the substrate surface, to affect an optimal silicon alloy induced strain in the substrate channel. In addition, the non-planar relationship may be selected so that any strains caused by different lattice spaced layers formed over the silicon alloy material have a reduced effect on the strain in the channel region.

摘要翻译： PMOS晶体管的沟道区域中的最佳应变由硅合金材料在与衬底表面非平面关系的器件的接合区域中提供。 选择硅合金材料，硅合金材料的尺寸以及硅合金材料与基板表面的非平面关系，使得硅合金材料的晶格间距与 衬底在衬底表面以下以及衬底表面之上的硅合金材料中引起应变，以影响衬底通道中最佳的硅合金诱导应变。 此外，可以选择非平面关系，使得由在硅合金材料上形成的不同格子间隔层引起的任何应变对通道区域中的应变具有降低的影响。

公开(公告)号：US20070004123A1

公开(公告)日：2007-01-04

申请号：US11173660

申请日：2005-06-30

申请人： Mark Bohr ,  Steven Keating ,  Thomas Letson ,  Anand Murthy ,  Donald O'Neill ,  Willy Rachmady

发明人： Mark Bohr ,  Steven Keating ,  Thomas Letson ,  Anand Murthy ,  Donald O'Neill ,  Willy Rachmady

IPC分类号： H01L21/8238

CPC分类号： H01L29/045 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.

摘要翻译： 实施例是改进的晶体管结构和制造该结构的方法。 特别地，实施例的湿蚀刻形成具有改进的尖端形状的源极和漏极区域，以通过改善短沟道效应的控制，增加饱和电流，改善冶金栅极长度的控制，增加载流子迁移率来提高晶体管的性能 并且在源极和漏极与硅化物之间的界面处降低接触电阻。

公开(公告)号：US07091615B2

公开(公告)日：2006-08-15

申请号：US11084638

申请日：2005-03-18

申请人： Ebrahim Andideh ,  Mark Bohr

发明人： Ebrahim Andideh ,  Mark Bohr

IPC分类号： H01L23/532

CPC分类号： H01L21/76822 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76807 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for forming an interlayer dielectric layer is disclosed. The method comprises first forming a carbon-doped oxide (CDO) layer with a first concentration of carbon dopants therein. Next, the CDO layer is further formed with a second concentration of carbon dopants therein, wherein the first concentration is different than the second concentration.

公开(公告)号：US20060046399A1

公开(公告)日：2006-03-02

申请号：US10925566

申请日：2004-08-25

申请人： Nick Lindert ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau ,  Mark Bohr ,  Anand Murthy

发明人： Nick Lindert ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau ,  Mark Bohr ,  Anand Murthy

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

摘要： A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.

摘要翻译： 栅极结构可以用作掩模以形成源区和漏区。 然后可以去除栅极结构以形成间隙，并且可以在间隙中形成间隔物以限定沟槽。 在将沟槽形成衬底的过程中，去除源极漏极区的一部分。 然后用外延材料填充衬底，并在其上形成新的栅极结构。 结果，可以实现更突然的源极漏极结。

公开(公告)号：US20060043579A1

公开(公告)日：2006-03-02

申请号：US10930247

申请日：2004-08-31

申请人： Jun He ,  Zhiyong Ma ,  Jose Maiz ,  Mark Bohr ,  Martin Giles ,  Guanghai Xu

发明人： Jun He ,  Zhiyong Ma ,  Jose Maiz ,  Mark Bohr ,  Martin Giles ,  Guanghai Xu

IPC分类号： H01L23/34

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L23/42 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00 ,  H01L2224/0401

摘要： A semiconductor substrate having metal oxide semiconductor (MOS) devices, such as an integrated circuit die, is mechanically coupled to a stress structure to apply a stress that improves the performance of at least a portion of the MOS devices on the die.

摘要翻译： 具有诸如集成电路管芯的金属氧化物半导体（MOS）器件的半导体衬底被机械耦合到应力结构，以施加提高模具上的至少一部分MOS器件的性能的应力。

公开(公告)号：US20050253192A1

公开(公告)日：2005-11-17

申请号：US10847987

申请日：2004-05-17

申请人： Ibrahim Ban ,  Bernhard Sell ,  Sanjay Natarajan ,  Mark Bohr

发明人： Ibrahim Ban ,  Bernhard Sell ,  Sanjay Natarajan ,  Mark Bohr

IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L29/6656 ,  H01L29/7833 ,  Y10S257/90

摘要： Embodiments of the invention provides a stepped tip junction region between a source/drain region of a transistor and a gate. In some embodiments, a spacer of the transistor includes a tip junction spacer layer and a source/drain spacer layer.

摘要翻译： 本发明的实施例提供了在晶体管的源极/漏极区域和栅极之间的阶梯形尖端结区域。 在一些实施例中，晶体管的间隔物包括尖端接合间隔层和源极/漏极间隔层。

公开(公告)号：US06933222B2

公开(公告)日：2005-08-23

申请号：US10336236

申请日：2003-01-02

申请人： Valery M. Dubin ,  Mark Bohr

发明人： Valery M. Dubin ,  Mark Bohr

IPC分类号： H01J1/02 ,  H01L21/3205 ,  H01L21/335 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/76 ,  B82Y10/00 ,  H01L21/768 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53276 ,  H01L29/66439 ,  H01L29/7613 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include the selective deposition of carbon nanotubes onto catalysts selectively formed on a conductive layer at the bottom of openings in a dielectric layer. The openings in the dielectric layer are formed using suitable techniques, such as, but not limited to, dielectric etching, and the formation of ring gate electrodes, including spacers, that provide openings for depositing self-aligned carbon nanotube semiconductor channels.

摘要翻译： 根据本发明的方法的实施例提供了三维碳纳米管（CNT）集成电路，其包括由电介质层分离的CNT阵列层，其中形成有介电层内的导电迹线以电连接各个CNT。 制造三维碳纳米管FET集成电路的方法包括将碳纳米管选择性沉积到选择性地形成在电介质层的开口底部的导电层上的催化剂上。 电介质层中的开口使用合适的技术形成，例如但不限于电介质蚀刻，以及形成包括间隔物的环形栅电极，其提供用于沉积自对准碳纳米管半导体通道的开口。

公开(公告)号：US20050148190A1

公开(公告)日：2005-07-07

申请号：US10746420

申请日：2003-12-24

申请人： Valery Dubin ,  Makarem Hussein ,  Mark Bohr

发明人： Valery Dubin ,  Makarem Hussein ,  Mark Bohr

IPC分类号： H01L21/311 ,  H01L21/316 ,  H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/31116 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/76807 ,  H01L21/76849

摘要： A damascene process using a doped and undoped oxide ILD is described. The selectivity between the carbon doped and carbon free oxide provides an etching stop between the ILD's in addition to providing mechanical strength to the structure.

摘要翻译： 描述了使用掺杂和未掺杂的氧化物ILD的镶嵌工艺。 碳掺杂和无碳氧化物之间的选择性除了为结构提供机械强度外，还提供ILD之间的蚀刻停止。

公开(公告)号：US20050062169A1

公开(公告)日：2005-03-24

申请号：US10668986

申请日：2003-09-22

申请人： Valery Dubin ,  Sridhar Balakrishnan ,  Mark Bohr

发明人： Valery Dubin ,  Sridhar Balakrishnan ,  Mark Bohr

IPC分类号： H01L21/288 ,  H01L21/60 ,  H01L23/485 ,  H01L23/48

CPC分类号： H01L24/13 ,  H01L21/288 ,  H01L21/4853 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11614 ,  H01L2224/13026 ,  H01L2224/13084 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13564 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/29111 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

摘要翻译： 与模具包装相关的方法，技术和结构。 在一个示例性实施例中，管芯封装互连结构包括半导体衬底和与半导体衬底接触的第一导电层。 第一导电层可以包括基底层金属。 基底层金属可以包括Cu。 示例性实施方式还可以包括与第一导电层接触的扩散阻挡层和在扩散阻挡层顶部的润湿层。 凸起层可以驻留在润湿层的顶部，其中凸起层可以包括Sn，并且Sn可以被电镀。 扩散阻挡层可以是无电解的并且可以适于防止Cu和Sn扩散通过扩散阻挡层。 此外，扩散阻挡层可以进一步适于抑制凸块层中的晶须型形成。

公开(公告)号：US06703685B2

公开(公告)日：2004-03-09

申请号：US10013075

申请日：2001-12-10

申请人： Shahriar Ahmed ,  Mark Bohr ,  Stephen Chambers ,  Richard Green

发明人： Shahriar Ahmed ,  Mark Bohr ,  Stephen Chambers ,  Richard Green

IPC分类号： H01L27082

CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821

摘要： The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

摘要翻译： 本发明涉及一种形成紧凑型双极结型晶体管（BJT）的方法，其包括形成邻近发射极堆叠的自对准集电极阱和隔离结构。 基底层由设置在基板中的外延硅形成。