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公开(公告)号：US07622162B1
公开(公告)日：2009-11-24
申请号：US11811048
申请日：2007-06-07
CPC分类号： C23C16/402 , C23C16/56 , H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/02348 , H01L21/3105 , H01L21/31608 , H01L21/67115 , H01L21/76224 , H01L29/7846
摘要： Using UV radiation, methods to modify shallow trench isolation (STI) film tensile stress to generate channel strain without adversely impacting the efficiency of the transistor fabrication process are disclosed. Methods involve a two phase process: a deposition phase, wherein silanol groups are formed in the silicon dioxide film, and a bond reconstruction phase, wherein UV radiation removes silanol bonds and induce tensile stress in the silicon dioxide film.
摘要翻译： 公开了使用UV辐射的方法来修改浅沟槽隔离（STI）膜拉伸应力以产生通道应变而不会不利地影响晶体管制造工艺的效率。 方法涉及两相工艺：沉积阶段，其中在二氧化硅膜中形成硅烷醇基团，以及键重建阶段，其中UV辐射消除硅烷醇键并引起二氧化硅膜中的拉伸应力。
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公开(公告)号：US20090286381A1
公开(公告)日：2009-11-19
申请号：US12122614
申请日：2008-05-16
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , C23C16/045 , C23C16/401 , H01L21/76801
摘要： In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps without damaging underlying features and little or no incidence of voids or weak spots is provided. A protective layer is deposited to protect underlying features in regions of the substrate having lower feature density so that unwanted material may be removed from regions of the substrate having higher feature density. This protective layer may deposits thicker on a low density feature than on a high density feature and may be deposited using a PECVD process or low sputter/deposition ratio HDP CVD process. This protective layer may also be a metallic oxide layer that is resistant to fluorine etching, such as zirconium oxide (ZrO2) or aluminum oxide (Al2O3).
摘要翻译： 可以填充高纵横比（通常至少6:1，例如7:1或更高），窄宽度（通常为0.13微米，例如0.1微米或更小）的间隙的原位半导体工艺，而不损坏底层特征和少量 或者不提供空隙或弱点的发生。 沉积保护层以保护具有较低特征密度的衬底区域中的底层特征，使得可以从具有较高特征密度的衬底的区域去除不需要的材料。 该保护层可以在低密度特征上比在高密度特征上沉积更厚，并且可以使用PECVD工艺或低溅射/沉积比HDP CVD工艺沉积。 该保护层也可以是耐氟蚀刻的金属氧化物层，例如氧化锆（ZrO 2）或氧化铝（Al 2 O 3）。
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公开(公告)号：US10037905B2
公开(公告)日：2018-07-31
申请号：US12646830
申请日：2009-12-23
IPC分类号： H01L21/67 , H01L21/02 , H01L21/3105 , H01L21/768
CPC分类号： H01L21/67115 , H01L21/02063 , H01L21/02074 , H01L21/3105 , H01L21/76814 , H01L21/76825 , H01L21/76826 , H01L21/76831 , H01L21/76877 , H01L21/76883
摘要： Treatment of carbon-containing low-k dielectric with UV radiation and a reducing agent enables process-induced damage repair. Also, treatment with a reducing agent and UV radiation is effective to clean a processed wafer surface by removal of metal oxide (e.g., copper oxide) and/or organic residue of CMP slurry from the planarized surface of a processed wafer with or without low-k dielectric. The methods of the invention are particularly applicable in the context of damascene processing to recover lost low-k property of a dielectric damaged during processing, either pre-metalization, post-planarization, or both, and/or provide effective post-planarization surface cleaning to improve adhesion of subsequently applied dielectric barrier and/or other layers.
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54.发明申请DUAL PLENUM, AXI-SYMMETRIC SHOWERHEAD WITH EDGE-TO-CENTER GAS DELIVERY 有权双层气体，AXI-SYMMETRIC SHOWERHEAD具有边缘到中心气体输送公开(公告)号：US20130341433A1
公开(公告)日：2013-12-26
申请号：US13531254
申请日：2012-06-22
申请人： Shambhu N. Roy , Vincent E. Burkhart , Natan Solomon , Sanjay Gopinath , Kaihan Abidi Ashtiani , Bart van Schravendijk , Jason Stevens , Dhritiman Subha Kashyap , David Cohen
发明人： Shambhu N. Roy , Vincent E. Burkhart , Natan Solomon , Sanjay Gopinath , Kaihan Abidi Ashtiani , Bart van Schravendijk , Jason Stevens , Dhritiman Subha Kashyap , David Cohen
IPC分类号： B05B1/14
CPC分类号： C23C16/45565 , C23C16/45574
摘要： A dual-plenum showerhead for semiconductor processing operations is provided. The showerhead may include a faceplate with two sets of gas distribution holes, each set fed by a separate plenum. One set of gas distribution holes may be through-holes in a faceplate of the showerhead and may allow gases trapped between the faceplate and a plasma dome to flow towards a wafer. The other set of gas distribution holes may distribute gas routed through passages or channels in the faceplate towards the wafer. The passages or channels in the faceplate may include radial channels and annular channels and may be fed from an annular gas distribution channel about the periphery of the faceplate.
摘要翻译： 提供了一种用于半导体加工操作的双通风淋浴喷头。 淋浴头可以包括具有两组气体分配孔的面板，每组由单独的增压室供给。 一组气体分配孔可以是喷头的面板中的通孔，并且可允许捕获在面板和等离子体圆顶之间的气体朝向晶片流动。 另一组气体分配孔可以将通过面板中的通道或通道的气体分配到晶片。 面板中的通道或通道可以包括径向通道和环形通道，并且可以从围绕面板周边的环形气体分配通道供给。
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公开(公告)号：US08430992B1
公开(公告)日：2013-04-30
申请号：US12763545
申请日：2010-04-20
IPC分类号： C23F1/00 , C23C16/00 , H01L21/306
CPC分类号： H01L21/76886 , H01L21/76831 , H01L21/76834 , H01L21/76846 , H01L21/76849 , H01L21/76856 , H01L21/76862 , H01L21/76867 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. In a Damascene interconnect, PSAB layer typically resides at an interface between the metal layer and a dielectric diffusion barrier layer. PSAB layers promote improved adhesion between a metal layer and an adjacent dielectric diffusion barrier layer. Further, PSAB layers can protect metal surfaces from inadvertent oxidation during fabrication process. A PSAB layer may be formed entirely within the top portion of a metal layer, by, for example, chemically converting metal surface to a thin layer of metal silicide. Thickness of PSAB layers, and, consequently resistance of interconnects can be controlled by partially passivating metal surface prior to formation of PSAB layer. Such passivation can be accomplished by controllably treating metal surface with a nitrogen-containing compound to convert metal to metal nitride.
摘要翻译： 保护性自对准缓冲层（PSAB）层是在部分制造的半导体器件中在金属层的表面选择性地形成的材料层。 在镶嵌互连中，PSAB层通常驻留在金属层和电介质扩散阻挡层之间的界面处。 PSAB层促进了金属层和相邻电介质扩散阻挡层之间的改善的附着力。 此外，PSAB层可以在制造过程中保护金属表面免于无意的氧化。 可以通过例如将金属表面化学转化成金属硅化物的薄层，完全在金属层的顶部内形成PSAB层。 PSAB层的厚度，因此互连电阻可以在形成PSAB层之前通过部分钝化金属表面来控制。 可以通过用含氮化合物可控地处理金属表面以将金属转化为金属氮化物来实现这种钝化。
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公开(公告)号：US08173537B1
公开(公告)日：2012-05-08
申请号：US11693617
申请日：2007-03-29
申请人： Kaushik Chattopadhyay , Keith Fox , Tom Mountsier , Hui-Jung Wu , Bart van Schravendijk , Kimberly Branshaw
发明人： Kaushik Chattopadhyay , Keith Fox , Tom Mountsier , Hui-Jung Wu , Bart van Schravendijk , Kimberly Branshaw
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L23/53295 , H01L21/6719 , H01L21/67201 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Stability of an underlying dielectric diffusion barrier during deposition and ultraviolet (UV) processing of an overlying dielectric layer is critical for successful integration. UV-resistant diffusion barrier layers are formed by depositing the layer in a hydrogen-starved environment. Diffusion barrier layers can be made more resistant to UV radiation by thermal, plasma, or UV treatment during or after deposition. Lowering the modulus of the diffusion barrier layer can also improve the resistance to UV radiation.
摘要翻译： 沉积期间的底层电介质扩散屏障和上覆介质层的紫外（UV）处理的稳定性对成功整合至关重要。 通过在氢饥饿环境中沉积该层而形成耐UV扩散阻挡层。 扩散阻挡层可以通过在沉积期间或之后的热，等离子体或UV处理更耐紫外线辐射。 降低扩散阻挡层的模量也可以提高耐UV辐射。
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公开(公告)号：US07622380B1
公开(公告)日：2009-11-24
申请号：US11245227
申请日：2005-10-06
IPC分类号： H01L21/44
CPC分类号： H01L21/76826 , H01L21/76808 , H01L21/76828 , H01L21/76832 , Y10S438/902
摘要： A method of improving adhesion between layers in the formation of a semiconductor device and integrated circuit, and the resultant intermediate semiconductor structure, which include a substrate layer with a low k insulating layer thereover. The low k insulating layer includes a treated surface area of adsorbed gaseous particles. This treated surface area is formed by flowing a gas, preferably, silane, disilane, dichlorosilane, germane or combinations thereof, over a surface of the heated low k insulating layer for adsorption of such gaseous particles onto the heated surface, wherein the insulating layer maintains its original thickness. A capping layer is then deposited directly over the insulating layer wherein the treated surface area of the insulating layer significantly improves adhesion between the insulating layers and the capping layers to prevent delamination therebetween during subsequent processing steps of forming the integrated circuit.
摘要翻译： 在半导体器件和集成电路的形成中提高层之间的粘合力的方法以及所得到的中间半导体结构，其包括其上具有低k绝缘层的衬底层。 低k绝缘层包括被吸附的气态颗粒的处理表面积。 该经处理的表面积是通过在加热的低k绝缘层的表面上流动气体，优选硅烷，乙硅烷，二氯硅烷，锗烷或其组合形成的，用于将这种气态颗粒吸附到加热表面上，其中绝缘层保持 其原始厚度。 然后将覆盖层直接沉积在绝缘层上，其中绝缘层的经处理的表面区域显着地改善了在形成集成电路的后续处理步骤期间在绝缘层和封盖层之间的粘附。
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58.发明授权公开(公告)号：US07052988B1
公开(公告)日：2006-05-30
申请号：US10773821
申请日：2004-02-05
申请人： Bart van Schravendijk , Ming Li , Jason Tian , Tom Mountsier , M. Ziaul Karim
发明人： Bart van Schravendijk , Ming Li , Jason Tian , Tom Mountsier , M. Ziaul Karim
IPC分类号： H01L21/44
CPC分类号： H01L21/02126 , C23C16/401 , G03F7/091 , H01L21/02274 , H01L21/0276 , H01L21/31144 , H01L21/31612
摘要： A nitrogen-free anti-reflective layer for use in semiconductor photolithography is fabricated in a chemical vapor deposition process, optionally plasma-enhanced, using a gaseous mixture of carbon, silicon, and oxygen sources. By varying the process parameters, acceptable values of the refractive index n and extinction coefficient k can be obtained. The nitrogen-free anti-reflective layer produced by this technique eliminates the mushrooming and footing problems found with conventional anti-reflective layers.
摘要翻译： 使用碳，硅和氧源的气体混合物，在化学气相沉积工艺（任选地等离子体增强）中制造用于半导体光刻中的无氮抗反射层。 通过改变工艺参数，可以获得折射率n和消光系数k的可接受值。 通过这种技术生产的无氮抗反射层消除了常规抗反射层发现的萌发和基础问题。
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公开(公告)号：US06972252B1
公开(公告)日：2005-12-06
申请号：US10647773
申请日：2003-08-25
IPC分类号： H01L21/44 , H01L21/768
CPC分类号： H01L21/76826 , H01L21/76808 , H01L21/76828 , H01L21/76832 , Y10S438/902
摘要： A method of improving adhesion between layers in the formation of a semiconductor device and integrated circuit, and the resultant intermediate semiconductor structure, which include a substrate layer with a low k insulating layer thereover. The low k insulating layer includes a treated surface area of adsorbed gaseous particles. This treated surface area is formed by flowing a gas, preferably, silane, disilane, dichlorosilane, germane or combinations thereof, over a surface of the heated low k insulating layer for adsorption of such gaseous particles onto the heated surface, wherein the insulating layer maintains its original thickness. A capping layer is then deposited directly over the insulating layer wherein the treated surface area of the insulating layer significantly improves adhesion between the insulating layers and the capping layers to prevent delamination therebetween during subsequent processing steps of forming the integrated circuit.
摘要翻译： 在半导体器件和集成电路的形成中提高层之间的粘合力的方法以及所得到的中间半导体结构，其包括其上具有低k绝缘层的衬底层。 低k绝缘层包括被吸附的气态颗粒的处理表面积。 该经处理的表面积是通过在加热的低k绝缘层的表面上流动气体，优选硅烷，乙硅烷，二氯硅烷，锗烷或其组合形成的，用于将这种气态颗粒吸附到加热表面上，其中绝缘层保持 其原始厚度。 然后将覆盖层直接沉积在绝缘层上，其中绝缘层的经处理的表面区域显着地改善了在形成集成电路的后续处理步骤期间在绝缘层和封盖层之间的粘附。
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60.发明授权公开(公告)号：US06846391B1
公开(公告)日：2005-01-25
申请号：US10035773
申请日：2001-12-21
IPC分类号： C23C16/04 , C23C16/507 , H01L21/316 , H01L21/762 , C23C14/00 , B44C1/22 , C03C15/00 , C23C14/32 , H05H1/02
CPC分类号： C23C16/045 , C23C16/401 , C23C16/509 , H01L21/02129 , H01L21/02164 , H01L21/02274 , H01L21/31612 , H01L21/76224
摘要： A process for filling high aspect ratio gaps on substrates uses conventional high density plasma deposition processes to deposit fluorine-doped films, with an efficient sputtering inert gas, such as Ar, replaced or reduced with an inefficient sputtering inert gas such as He and/or hydrogen. By reducing the sputtering component, sidewall deposition from the sputtered material is reduced. Consequently, gaps with aspect ratios greater than 3.0:1 and spacings between lines less than 0.13 microns can be filled with low dielectric constant films without the formation of voids and without damaging circuit elements.
摘要翻译： 用于在衬底上填充高纵横比间隙的方法使用常规的高密度等离子体沉积工艺沉积氟掺杂的膜，利用诸如Ar的有效溅射惰性气体（例如Ar）被替换或还原，其中诸如He和/或 氢。 通过减少溅射部件，减少了来自溅射材料的侧壁沉积。 因此，宽高比大于3.0:1的间隙和小于0.13微米的线之间的间距可以用低介电常数膜填充而不形成空隙并且不损坏电路元件。
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