公开(公告)号：US08912518B2

公开(公告)日：2014-12-16

申请号：US13671824

申请日：2012-11-08

Applicant: Intermolecular, Inc.

Inventor： David Chi ,  Vidyut Gopal ,  Minh Huu Le ,  Minh Anh Nguyen ,  Dipankar Pramanik ,  Milind Weling

IPC: H01L29/02 ,  H01L47/00 ,  G11C11/00 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L45/145 ,  G11C13/0007 ,  G11C2213/32 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/146 ,  H01L45/1616

Abstract: Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from doped metal oxides and/or nitrides. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature annealing. In some embodiments, the breakdown voltage of a current limiting layer may be at least about 8V. Some examples of such current limiting layers include titanium oxide doped with niobium, tin oxide doped with antimony, and zinc oxide doped with aluminum. Dopants and base materials may be deposited as separate sub-layers and then redistributed by annealing or may be co-deposited using reactive sputtering or co-sputtering. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layer while maintaining their performance.

Abstract translation: 提供了诸如电阻随机存取存储器（ReRAM）单元的半导体器件，其包括由掺杂的金属氧化物和/或氮化物形成的限流层。 这些限流层可具有至少约1欧姆 - 厘米的电阻率。 即使当这些层受到强电场和/或高温退火时，也保持该电阻率水平。 在一些实施例中，限流层的击穿电压可以为至少约8V。 这种电流限制层的一些实例包括掺杂有铌的氧化钛，掺杂有锑的氧化锡和掺杂有铝的氧化锌。 掺杂剂和基材可以作为单独的子层沉积，然后通过退火重新分布，或者可以使用反应溅射或共溅射共沉积。 层的高电阻率允许在保持其性能的同时缩小包括这些层的半导体器件的尺寸。

公开(公告)号：US20140353566A1

公开(公告)日：2014-12-04

申请号：US13903656

申请日：2013-05-28

Applicant: Intermolecular Inc. ,  SanDisk 3D LLC ,  Kabushiki Kaisha Toshiba

Inventor： Yun Wang ,  Tony P. Chiang ,  Dipankar Pramanik

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/1616 ,  H01L45/1641

Abstract: A switching element for resistive-switching memory (ReRAM) provides a controllable, consistent filament break-point at an abrupt structural discontinuity between a layer of high-k high-ionicity variable-resistance (VR) material and a layer of low-k low-ionicity VR material. The high-ionicity layer may be crystalline and the low-ionicity layer may be amorphous. The consistent break-point and characteristics of the low-ionicity layer facilitate lower-power operation. The defects (e.g., oxygen or nitrogen vacancies) that constitute the filament originate either in the high-ionicity VR layer or in a source electrode. The electrode nearest to the low-ionicity layer may be intrinsically inert or may be rendered effectively inert. Some electrodes are rendered effectively inert by the creation of the low-ionicity layer over the electrode.

Abstract translation: 用于电阻式开关存储器（ReRAM）的开关元件在高k高离子度可变电阻（VR）材料层和低k低电平层之间突然的结构不连续性时提供可控的一致的灯丝断裂点 活性VR材料。 高离子层可以是结晶的，低离子层可以是无定形的。 低离子层的一致性断点和特性有利于低功率运行。 构成长丝的缺陷（例如，氧或氮空位）起源于高离子性VR层或源电极。 最接近低离子层的电极本质上是惰性的，或者可以有效地使其成为惰性的。 通过在电极上产生低离子层，使一些电极变得有效地是惰性的。

公开(公告)号：US08871601B2

公开(公告)日：2014-10-28

申请号：US13728934

申请日：2012-12-27

Applicant: Intermolecular, Inc.

Inventor： Xuena Zhang ,  Mankoo Lee ,  Dipankar Pramanik

IPC: H01L21/331 ,  H01L21/44 ,  H01L23/538 ,  H01L21/768 ,  H01L23/532 ,  B82Y10/00 ,  B82Y30/00

CPC classification number: H01L23/538 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76873 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention include diffusion barriers, methods for forming the barriers, and semiconductor devices utilizing the barriers. The diffusion barrier comprises a self-assembled monolayer (SAM) on a semiconductor substrate, where one surface of the SAM is disposed in contact with and covalently bonded to the semiconductor substrate, and one surface of the monolayer is disposed in contact with and covalently bonded to a metal layer. In some embodiments, the barrier comprises an assembly of one or more monomeric subunits of the following structure: Si—(CnHy)-(LM)m where n is from 1 to 20, y is from 2n−2 to 2n, m is 1 to 3, L is a Group VI element, and M is a metal, such as copper. In some embodiments, (CnHy) can be branched, crosslinked, or cyclic.

Abstract translation: 本发明的实施例包括扩散阻挡层，形成屏障的方法以及利用屏障的半导体器件。 扩散阻挡层包括在半导体衬底上的自组装单层（SAM），其中SAM的一个表面设置成与半导体衬底接触并且共价键合到半导体衬底，并且单层的一个表面被设置成接触并共价键合 到金属层。 在一些实施方案中，阻挡层包含一个或多个下列结构的单体亚单位的组合：Si-（CnHy） - （LM）m，其中n为1至20，y为2n-2至2n，m为1 至3，L为VI族元素，M为金属，例如铜。 在一些实施方案中，（C n H y）可以是支链，交联或环状的。

公开(公告)号：US20140299056A1

公开(公告)日：2014-10-09

申请号：US14308846

申请日：2014-06-19

Applicant: Intermolecular Inc.

Inventor： Philip Kraus ,  Boris Borisov ,  Dipankar Pramanik

IPC: C23C16/455 ,  C23C16/42 ,  C23C16/48

CPC classification number: C23C16/45551 ,  C23C16/42 ,  C23C16/4554 ,  C23C16/483 ,  C30B25/12 ,  C30B29/06 ,  C30B29/08 ,  H01L21/02532 ,  H01L21/0262

Abstract: Epitaxial films are grown by alternately exposed to precursor dosing regions, inert gas plasma regions, hydrogen-containing plasma regions, chlorine-containing plasma and metrology regions, or regions where an atomic hydrogen source is located. Alternately, laser irradiation techniques may be substituted for the plasma energy in some of the processing regions. The film growth process can be implemented at substrate temperatures between about 25 C and about 600 C, together with optional exposures to laser irradiation to cause the surface of the film to melt or to experience a near-melt condition.

Abstract translation: 外延膜通过交替地暴露于前体给料区域，惰性气体等离子体区域，含氢等离子体区域，含氯等离子体和计量区域或原子氢源所在的区域而生长。 或者，激光照射技术可以替代一些处理区域中的等离子体能量。 膜生长过程可以在约25℃至约600℃之间的衬底温度下进行，以及可选地暴露于激光照射以使膜的表面熔化或经历近熔融状态。

公开(公告)号：US20140273300A1

公开(公告)日：2014-09-18

申请号：US14072611

申请日：2013-11-05

Applicant: Intermolecular, Inc.

Inventor： Dipankar Pramanik ,  Tony P. Chiang

IPC: H01L45/00 ,  H01L21/66

CPC classification number: H01L27/2418 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/77 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/283 ,  H01L21/324 ,  H01L22/12 ,  H01L22/34 ,  H01L27/24 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/00 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/144 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1641 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Forming a resistive memory structure at a temperature well above the operating temperature can reduce the forming voltage and create a defect distribution with higher stability and lower programming voltages. The forming temperature can be up to 200 C above the operating temperature. The memory chip can include an embedded heater in the chip package, allowing for a chip forming process after packaging.

Abstract translation: 在远高于工作温度的温度下形成电阻式存储器结构可以降低成型电压并产生具有更高稳定性和较低编程电压的缺陷分布。 成型温度高于工作温度200℃。 存储芯片可以包括芯片封装中的嵌入式加热器，从而允许封装后的芯片形成工艺。

公开(公告)号：US20140262749A1

公开(公告)日：2014-09-18

申请号：US13804265

申请日：2013-03-14

Applicant: Intermolecular, Inc.

Inventor： Ashish Bodke ,  Olov Karlsson ,  Kevin Kashefi ,  Chi-I Lang ,  Dipankar Pramanik ,  Hong Sheng Yang ,  Xuena Zhang

IPC: C23C14/35

CPC classification number: B01J19/0046 ,  B01J2219/0043 ,  B01J2219/00443 ,  B01J2219/00527 ,  B01J2219/00635 ,  B01J2219/0075 ,  B01J2219/00756 ,  C23C14/042 ,  C23C14/345

Abstract: Combinatorial processing of a substrate comprising site-isolated sputter deposition and site-isolated plasma processing can be performed in a same process chamber. The process chamber, configured to perform sputter deposition and plasma processing, comprises a grounded shield having at least an aperture disposed above the substrate to form a small, dark space gap to reduce or eliminate any plasma formation within the gap. The plasma processing may include plasma etching or plasma surface treatment.

Abstract translation: 包含现场分离的溅射沉积和位置分离等离子体处理的基板的组合处理可以在相同的处理室中进行。 被配置为执行溅射沉积和等离子体处理的处理室包括接地屏蔽，其具有设置在衬底上方的至少一个孔，以形成小的，较暗的空间间隙，以减少或消除间隙内的任何等离子体形成。 等离子体处理可以包括等离子体蚀刻或等离子体表面处理。

公开(公告)号：US20140186617A1

公开(公告)日：2014-07-03

申请号：US13728889

申请日：2012-12-27

Applicant: INTERMOLECULAR, INC.

Inventor： Xuena Zhang ,  Dipankar Pramanik

IPC: C03C17/36 ,  C03C17/00

CPC classification number: C03C17/36 ,  C03C17/3636 ,  C03C17/3644 ,  Y10T428/261 ,  Y10T428/265 ,  Y10T428/31612 ,  Y10T428/31678

Abstract: Embodiments of the present invention include low emissivity (low-E) coatings and methods for forming the coatings. The low-E coating comprises a self-assembled monolayer (SAM) on a glass substrate, where one surface of the SAM is disposed in contact with and covalently bonded to the glass substrate, and one surface of the monolayer is disposed in contact with and covalently bonded to a metal layer. In some embodiments, the low-E coating comprises an assembly of one or more monomeric subunits of the following structure: Si—(CnHy)-(LM)m where n is from 1 to 20, y is from 2n-2 to 2n, m is 1 to 3, L is a Group VI element, and M is a metal, such as silver. In some embodiments, (CnHy) can be branched, crosslinked, or cyclic. The coating can further comprise an antireflection coating on the metal layer.

Abstract translation: 本发明的实施例包括低发射率（低E）涂层和形成涂层的方法。 低E涂层包括在玻璃基板上的自组装单层（SAM），其中SAM的一个表面设置成与玻璃基板接触并共价结合到玻璃基板上，单层的一个表面设置成与 共价键合到金属层。 在一些实施方案中，低E涂层包含以下结构的一个或多个单体亚单位的组合：Si-（CnHy） - （LM）m，其中n为1至20，y为2n-2至2n， m为1〜3，L为VI族元素，M为银等金属。 在一些实施方案中，（C n H y）可以是支链，交联或环状的。 涂层还可以包括在金属层上的抗反射涂层。

公开(公告)号：US20140183737A1

公开(公告)日：2014-07-03

申请号：US13728934

申请日：2012-12-27

Applicant: INTERMOLECULAR, INC.

Inventor： Xuena Zhang ,  Mankoo Lee ,  Dipankar Pramanik

IPC: H01L23/538 ,  H01L21/768

CPC classification number: H01L23/538 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76873 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention include diffusion barriers, methods for forming the barriers, and semiconductor devices utilizing the barriers. The diffusion barrier comprises a self-assembled monolayer (SAM) on a semiconductor substrate, where one surface of the SAM is disposed in contact with and covalently bonded to the semiconductor substrate, and one surface of the monolayer is disposed in contact with and covalently bonded to a metal layer. In some embodiments, the barrier comprises an assembly of one or more monomeric subunits of the following structure: Si—(CnHy) (LM), where n is from 1 to 20, y is from 2n−2 to 2n, m is 1 to 3, L is a Group VI element, and M is a metal, such as copper. In some embodiments, (CnHy) can be branched, crosslinked, or cyclic.

Abstract translation: 本发明的实施例包括扩散阻挡层，形成屏障的方法以及利用屏障的半导体器件。 扩散阻挡层包括在半导体衬底上的自组装单层（SAM），其中SAM的一个表面设置成与半导体衬底接触并且共价键合到半导体衬底，并且单层的一个表面被设置成接触并共价键合 到金属层。 在一些实施方案中，阻挡层包含一个或多个下列结构的单体亚单位的组合：Si-（CnHy）（LM），其中n为1至20，y为2n-2至2n，m为1至 3，L是VI族元素，M是金属，例如铜。 在一些实施方案中，（C n H y）可以是支链，交联或环状的。

公开(公告)号：US20140183664A1

公开(公告)日：2014-07-03

申请号：US13728026

申请日：2012-12-27

Applicant: INTERMOLECULAR, INC.

Inventor： Sergey Barabash ,  Dipankar Pramanik ,  Xuena Zhang

IPC: H01L29/51 ,  H01L29/40

CPC classification number: H01L29/401 ,  B82Y10/00 ,  H01L21/28255 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66181 ,  H01L29/78 ,  H01L29/94

Abstract: A doped fullerene-based conductive material can be used as an electrode, which can contact a dielectric such as a high k dielectric. By aligning the dielectric with the band gap of the doped fullerene-based electrode, e.g., the conduction band minimum of the dielectric falls into one of the band gaps of the doped fullerene-based material, thermionic leakage through the dielectric can be reduced, since the excited electrons or holes in the electrode would need higher thermal excitation energy to overcome the band gap before passing through the dielectric layer.

Abstract translation: 可以使用掺杂的富勒烯类导电材料作为电极，其可以与诸如高k电介质的电介质接触。 通过将电介质与掺杂的富勒烯类电极的带隙对准，例如，电介质的导带最小值落入掺杂的富勒烯类材料的带隙之一中，可以减少通过电介质的热离子泄漏，因为 电极中的激发的电子或空穴将需要更高的热激发能量以克服通过介电层之前的带隙。

公开(公告)号：US20140179123A1

公开(公告)日：2014-06-26

申请号：US13722624

申请日：2012-12-20

Applicant: INTERMOLECULAR, INC.

Inventor： Ed Korczynski ,  Dipankar Pramanik

IPC: H01L21/263 ,  H05B6/00

CPC classification number: H05B1/0233 ,  H01L21/2686 ,  H01L21/67115 ,  H01L21/67253

Abstract: Methods and apparatus are described that allow the investigation of process variables used in RTP systems to be varied in a combinatorial manner across a plurality of site-isolated regions designated in the surface of a substrate. The methods and apparatus allow process variables such as power, dwell time, light source, cooling gas composition, cooling gas flow rate, reactive gas composition, reactive gas flow rate, and substrate support temperature and the like to be investigated.

Abstract translation: 描述了允许在RTP系统中使用的过程变量的研究以组合方式跨越在衬底的表面中指定的多个位置隔离区域的方式和装置。 该方法和装置允许研究诸如功率，停留时间，光源，冷却气体组成，冷却气体流速，反应气体组成，反应气体流速和衬底支撑温度等过程变量。