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    PROGRAMMING MEMORIES WITH MULTI-LEVEL PASS SIGNAL
    51.
    发明申请
    PROGRAMMING MEMORIES WITH MULTI-LEVEL PASS SIGNAL 审中-公开

    公开(公告)号：US20180190347A1

    公开(公告)日：2018-07-05

    申请号：US15907826

    申请日：2018-02-28

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Shyam Sunder Raghunathan ,  Pranav Kalavade ,  Krishna K. Parat ,  Charan Srinivasan

    IPC: G11C11/56 ,  G11C16/34 ,  G11C16/04 ,  G11C16/12

    CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3427

    Abstract: Methods of operating a memory include applying a first voltage level to control gates of a plurality of memory cells selected to be programmed while applying a second voltage level to a respective data line for each memory cell of the plurality of memory cells; increasing the voltage level applied to the respective data line for memory cells of a first subset of memory cells to a third voltage level then increasing the voltage level applied to the control gates of the plurality of memory cells to a fourth voltage level; increasing the voltage level applied to the respective data line for each memory cell of a second subset of memory cells of the plurality of memory cells to a fifth voltage level then; and after increasing the voltage level applied to the respective data line for each memory cell of the second subset of memory cells to the fifth voltage level, increasing the voltage level applied to the control gates of the plurality of memory cells to a sixth voltage level.

    Vertical memory cell string with dielectric in a portion of the body
    56.
    发明授权
    Vertical memory cell string with dielectric in a portion of the body 有权
    在身体的一部分具有电介质的垂直记忆单元格串

    公开(公告)号：US09437608B2

    公开(公告)日：2016-09-06

    申请号：US14581774

    申请日：2014-12-23

    Applicant: Micron Technology, Inc.

    Inventor： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

    IPC: H01L29/49 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L29/408 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

    Abstract: Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed.

    Abstract translation: 一些实施例包括具有主体的存储单元串，该主体具有在其中延伸并与源极/漏极接触的通道，与主体相邻的选择栅极，与主体相邻的多个访问线，以及在该部分中的电介质 源极/漏极与对应于与选择栅极最相邻的多条访问线路的端部相对应的电平。 身体部分中的电介质不会沿着身体的整个长度延伸。 描述和要求保护其他实施例。

    VERTICAL MEMORY CELL STRING WITH DIELECTRIC IN A PORTION OF THE BODY
    58.
    发明申请
    VERTICAL MEMORY CELL STRING WITH DIELECTRIC IN A PORTION OF THE BODY 有权
    垂直存储单元，具有介电体部分

    公开(公告)号：US20150108560A1

    公开(公告)日：2015-04-23

    申请号：US14581774

    申请日：2014-12-23

    Applicant: Micron Technology, Inc.

    Inventor： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

    IPC: H01L27/115

    CPC classification number: H01L29/408 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

    Abstract: Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed.

    Abstract translation: 一些实施例包括具有主体的存储单元串，该主体具有在其中延伸并与源极/漏极接触的通道，与主体相邻的选择栅极，与主体相邻的多个访问线，以及在该部分中的电介质 源极/漏极与对应于与选择栅极最相邻的多条访问线路的端部相对应的电平。 身体部分中的电介质不会沿着身体的整个长度延伸。 描述和要求保护其他实施例。

    APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN MEMORY OPERATIONS
    60.
    发明申请
    APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN MEMORY OPERATIONS 有权
    用于控制存储器操作中的身体潜力的装置和方法

    公开(公告)号：US20140160851A1

    公开(公告)日：2014-06-12

    申请号：US13707067

    申请日：2012-12-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

    IPC: G11C16/06

    CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

    Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

    Abstract translation: 一些实施例包括具有存储单元串的装置和方法，所述存储单元串包括位于装置的不同级别中的存储器单元和耦合到存储单元串的数据线。 存储单元串包括与存储单元相关联的柱体。 这种装置中的至少一个可以包括被配置为在存储器单元之间存储信息到存储器单元中的模块和/或确定存储器单元中存储在存储单元中的信息的值。 该模块还可以被配置为向数据线和/或源施加具有正值的电压以控制身体的电位。 描述其他实施例。

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