公开(公告)号：US20210296155A1

公开(公告)日：2021-09-23

申请号：US17340477

申请日：2021-06-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar ,  Zeev Wurman

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16

Abstract: A 3D semiconductor device, the device comprising: a first level comprising a single crystal layer, first transistors and a first metal layer; memory control circuits comprising said first transistors; a second level disposed above said first level, said second level comprising second transistors; a third level disposed above said second level, said third level comprising a plurality of third transistors; wherein said third transistors are aligned to said first transistors with a less than 40 nm alignment error, wherein said second level comprises a plurality of first memory cells, wherein said third level comprises a plurality of second memory cells, wherein one of said second transistors is at least partially self-aligned to at least one of said third transistors, being processed following a same lithography step, wherein at least one of said second memory cells comprises at least one of said third transistors, wherein said memory cells comprise a NAND non-volatile memory type.

公开(公告)号：US11106853B1

公开(公告)日：2021-08-31

申请号：US17306948

申请日：2021-05-04

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: G06F30/392 ,  G06F30/394

Abstract: A method of designing a 3D Integrated Circuit, the method comprising: performing partitioning to at least a logic strata comprising logic and a memory strata comprising memory; then performing a first placement of said logic strata using a 2D placer executed by a computer, wherein said 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices, wherein said 3D Integrated Circuit comprises through silicon vias for connection between said logic strata and said memory strata; and performing a second placement of said memory strata based on said first placement, wherein said memory comprises a first memory array, wherein said logic comprises a first logic circuit controlling said first memory array, wherein said first placement comprises placement of said first logic circuit, and wherein said second placement comprises placement of said first memory array based on said placement of said first logic circuit.

公开(公告)号：US10354995B2

公开(公告)日：2019-07-16

申请号：US15922913

申请日：2018-03-16

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Zeev Wurman

IPC: H01L29/45 ,  G06F9/00 ,  B82Y10/00 ,  H01L21/84 ,  H01L23/00 ,  H01L23/48 ,  H01L27/02 ,  H01L27/06 ,  H01L27/11 ,  H01L27/12 ,  H01L27/24 ,  H01L29/06 ,  H01L29/66 ,  H01L21/268 ,  H01L21/762 ,  H01L21/822 ,  H01L23/367 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/786 ,  H01L29/423 ,  H01L27/088 ,  H01L27/118 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/112 ,  H01L27/108 ,  H01L27/105 ,  H01L23/544 ,  G03F9/00 ,  H01L27/1157 ,  H01L29/775 ,  H01L21/8234

Abstract: A semiconductor device including: a first layer including a first memory cell, the first memory cell including a first transistor; a second layer including a second memory cell, the second memory cell including a second transistor; a periphery layer including a memory peripherals transistor, the periphery layer is disposed underneath the first layer; a memory including at least the first memory cell and the second memory cell, where the second memory cell overlays the first memory cell, where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where a peripherals circuit includes the memory peripherals transistor and controls the memory; a first external connections underlying the periphery layer, the first external connections includes connections from the device to a first external device; and a second external connections overlying the second layer, the second external connections includes connections from the device to a second external device.

公开(公告)号：US10127344B2

公开(公告)日：2018-11-13

申请号：US14672202

申请日：2015-03-29

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: G06F17/50

Abstract: A method of designing a 3D Integrated Circuit, the method including: performing partitioning to at least a first strata and a second strata; then performing a first placement of the first strata using a 2D placer executed by a computer, where the 2D placer is a Computer Aided Design (CAD) tool currently used in the industry for two-dimensional devices; and performing a second placement of the second strata based on the first placement, where the partitioning includes a partition between logic and memory, and where the logic includes at least one decoder representation for the memory.

公开(公告)号：US20180204835A1

公开(公告)日：2018-07-19

申请号：US15922913

申请日：2018-03-16

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Zeev Wurman

IPC: H01L27/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/45 ,  H01L29/423 ,  H01L27/12 ,  H01L27/118 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/112 ,  H01L27/11 ,  H01L27/108 ,  H01L27/105 ,  H01L27/088 ,  H01L27/02 ,  H01L23/544 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L23/367 ,  H01L21/84 ,  H01L21/822 ,  H01L21/762 ,  G03F9/00 ,  H01L21/268 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L27/0688 ,  B82Y10/00 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/268 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/84 ,  H01L23/367 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66272 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66901 ,  H01L29/775 ,  H01L29/78639 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/78696 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/80001 ,  H01L2924/00 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025

Abstract: A semiconductor device including: a first layer including a first memory cell, the first memory cell including a first transistor; a second layer including a second memory cell, the second memory cell including a second transistor; a periphery layer including a memory peripherals transistor, the periphery layer is disposed underneath the first layer; a memory including at least the first memory cell and the second memory cell, where the second memory cell overlays the first memory cell, where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where a peripherals circuit includes the memory peripherals transistor and controls the memory; a first external connections underlying the periphery layer, the first external connections includes connections from the device to a first external device; and a second external connections overlying the second layer, the second external connections includes connections from the device to a second external device.

公开(公告)号：US09941332B2

公开(公告)日：2018-04-10

申请号：US15409740

申请日：2017-01-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Zeev Wurman

IPC: H01L27/10 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00 ,  H01L29/04 ,  H01L29/167 ,  H01L29/78 ,  H01L29/66 ,  H01L27/105 ,  H01L21/02 ,  H01L21/324 ,  H01L21/223 ,  H01L21/311

CPC classification number: H01L27/2436 ,  G11C13/0021 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/2236 ,  H01L21/31116 ,  H01L21/324 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/249 ,  H01L29/04 ,  H01L29/167 ,  H01L29/66568 ,  H01L29/78 ,  H01L29/78696 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1616 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/00011 ,  H01L2224/80001

Abstract: A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor overlaying the second transistor or underneath the first transistor, where the second memory cell overlays the first memory cell, and where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.

公开(公告)号：US09887203B2

公开(公告)日：2018-02-06

申请号：US15222832

申请日：2016-07-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H03K19/173 ,  H01L27/112 ,  H01L23/525

CPC classification number: H01L27/1128 ,  G06F17/505 ,  G06F17/5068 ,  H01L21/768 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/1305 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/1778 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A 3D semiconductor device including: a first layer including a first monocrystalline layer, the first layer including first logic cells; a second layer including a monocrystalline semiconductor layer, the second layer overlying the first layer, the second layer including second transistors, where the logic cells include a Look-Up-Table logic cell, and where the second transistors are aligned to the first logic cells with less than 200 nm alignment error.

公开(公告)号：US09853089B2

公开(公告)日：2017-12-26

申请号：US15224929

申请日：2016-08-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Zeev Wurman

IPC: H01L27/24 ,  G11C13/00 ,  G03F9/00 ,  H01L21/822 ,  H01L21/84 ,  H01L23/544 ,  H01L21/762 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L45/00 ,  H01L23/48

CPC classification number: H01L27/2436 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/00011 ,  H01L2224/80001

Abstract: A semiconductor device, including: a first memory cell including a first transistor; a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor self-aligned to the first transistor; and a plurality of junctionless transistors, where at least one of the junctionless transistors controls access to at least one of the memory cells.

公开(公告)号：US20170221761A1

公开(公告)日：2017-08-03

申请号：US15488514

申请日：2017-04-16

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Zeev Wurman

IPC: H01L21/77 ,  H01L27/10 ,  H01L27/02 ,  H01L23/00 ,  H01L23/31 ,  H01L29/66 ,  H01L23/40

CPC classification number: H01L21/77 ,  B82Y10/00 ,  G11C16/0408 ,  G11C16/0483 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/4012 ,  H01L23/5286 ,  H01L24/01 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/1203 ,  H01L27/2436 ,  H01L27/249 ,  H01L28/00 ,  H01L29/1033 ,  H01L29/66257 ,  H01L29/6659 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/7881 ,  H01L29/792 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2221/6835 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the third transistor is controlled by a third control line, where the second transistor is overlaying the first transistor and the second transistor is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and the third control line, and where the second transistor and the third transistor are self-aligned.

公开(公告)号：US09691760B2

公开(公告)日：2017-06-27

申请号：US15089394

申请日：2016-04-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H03K19/096 ,  H01L27/06 ,  H03K19/177 ,  H03K3/037 ,  H01L23/522 ,  H01L23/525 ,  H01L23/367

CPC classification number: H01L27/0688 ,  H01L23/3677 ,  H01L23/5226 ,  H01L23/5252 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H03K3/0375 ,  H03K19/096 ,  H03K19/1774 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure, where the device includes a Phase Lock Loop (“PLL”) circuit, where the second clock distribution structure is connected to the Phase Lock Loop (“PLL”) circuit, and where the second transistors are aligned to the first transistors with less than 200 nm alignment error.