公开(公告)号：US10163755B2

公开(公告)日：2018-12-25

申请号：US15498321

申请日：2017-04-26

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L21/52 ,  H01L21/54 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/44 ,  H01L25/00 ,  H01L25/18 ,  H01L23/053 ,  H01L23/367 ,  H01L23/373

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

公开(公告)号：US20180158751A1

公开(公告)日：2018-06-07

申请号：US15874406

申请日：2018-01-18

Applicant: Micron Technology, Inc.

Inventor： Steven Groothuis ,  Jian Li ,  Shijian Luo

IPC: H01L23/367 ,  H01L25/065 ,  H01L21/56 ,  H01L23/48 ,  H01L21/48

CPC classification number: H01L23/3675 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/13 ,  H01L23/367 ,  H01L23/481 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/18161 ,  H01L2924/00

Abstract: Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. Electrical connectors may extend directly from the uppermost semiconductor die to the substrate.

公开(公告)号：US09818625B2

公开(公告)日：2017-11-14

申请号：US15059076

申请日：2016-03-02

Applicant: Micron Technology, Inc.

Inventor： Jian Li ,  Steven K. Groothuis ,  Michel Koopmans

IPC: H01L21/48 ,  H01L23/42 ,  H01L21/56 ,  H01L23/373 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/36 ,  H01L23/433 ,  H01L23/538 ,  H01L23/31 ,  H01L23/427 ,  H01L23/498

CPC classification number: H01L21/4882 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3731 ,  H01L23/3738 ,  H01L23/42 ,  H01L23/4275 ,  H01L23/4334 ,  H01L23/49827 ,  H01L23/5385 ,  H01L24/09 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16257 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311

Abstract: Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a thermally conductive casing defining a cavity, a stack of first semiconductor dies within the cavity, and a second semiconductor die stacked relative to the stack of first dies and carried by a package substrate. The semiconductor die assembly further includes a thermal spacer disposed between the package substrate and the thermally conductive casing. The thermal spacer can include a semiconductor substrate and plurality of conductive vias extending through the semiconductor substrate and electrically coupled to the stack of first semiconductor dies, the second semiconductor die, and the package substrate.

公开(公告)号：US20170229439A1

公开(公告)日：2017-08-10

申请号：US15498321

申请日：2017-04-26

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/373 ,  H01L23/00 ,  H01L23/44 ,  H01L25/18 ,  H01L23/367

CPC classification number: H01L23/44 ,  H01L21/50 ,  H01L21/52 ,  H01L21/54 ,  H01L21/563 ,  H01L23/04 ,  H01L23/053 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/3736 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/1134 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8388 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/156 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1815 ,  H01L2924/0715 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

公开(公告)号：US20170117205A1

公开(公告)日：2017-04-27

申请号：US15401762

申请日：2017-01-09

Applicant: Micron Technology, Inc.

Inventor： Steven Groothuis ,  Jian Li ,  Shijian Luo

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/48 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/3675 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/13 ,  H01L23/367 ,  H01L23/481 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/18161 ,  H01L2924/00

Abstract: Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. Electrical connectors may extend directly from the uppermost semiconductor die to the substrate. A heat sink may be located on a side of the uppermost semiconductor die opposite the substrate. A passivation material may be located between the uppermost semiconductor die and the heat sink.

公开(公告)号：US20160343639A1

公开(公告)日：2016-11-24

申请号：US14720015

申请日：2015-05-22

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li

IPC: H01L23/467 ,  F28D15/04 ,  H01L25/00 ,  H01L21/48 ,  H01L23/373 ,  H01L25/18

CPC classification number: F28D15/043 ,  F28D15/0233 ,  F28D15/0266 ,  F28D15/046 ,  H01L23/3675 ,  H01L23/427 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die, a second semiconductor die at a base region of the first die, and a thermal transfer device attached to a peripheral region of the first die and extending over the second die. The thermal transfer device includes a conductive structure having an internal cavity and a working fluid at least partially filling the cavity. The conductive structure further includes first and second fluid conversion regions adjacent the cavity. The first fluid conversion region transfers heat from at least the peripheral region of the first die to a volume of the working fluid to vaporize the volume in the cavity, and the second fluid conversion region condenses the volume of the working fluid in the cavity after it has been vaporized.

Abstract translation: 本文公开了具有层叠半导体管芯和包括蒸气室的热传递装置的半导体器件组件。 在一个实施例中，半导体器件组件包括第一半导体管芯，在第一管芯的基极区域的第二半导体管芯，以及附接到第一管芯的周边区域并在第二管芯上延伸的热传递器件。 热转印装置包括具有至少部分地填充空腔的内部空腔和工作流体的导电结构。 导电结构还包括邻近空腔的第一和第二流体转换区域。 第一流体转换区域将热量从第一模具的至少周边区域传递到工作流体的体积，以使空腔中的体积蒸发，并且第二流体转换区域使其中的空腔中的工作流体的体积冷凝 已蒸发。

公开(公告)号：US09287240B2

公开(公告)日：2016-03-15

申请号：US14105940

申请日：2013-12-13

Applicant: Micron Technology, Inc.

Inventor： Jian Li ,  Steven K. Groothuis ,  Michel Koopmans

IPC: H01L23/373 ,  H01L25/065 ,  H01L23/36 ,  H01L23/42 ,  H01L23/433 ,  H01L23/538 ,  H01L23/31 ,  H01L23/427 ,  H01L23/498

CPC classification number: H01L21/4882 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3731 ,  H01L23/3738 ,  H01L23/42 ,  H01L23/4275 ,  H01L23/4334 ,  H01L23/49827 ,  H01L23/5385 ,  H01L24/09 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16257 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311

Abstract: Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a thermally conductive casing defining a cavity, a stack of first semiconductor dies within the cavity, and a second semiconductor die stacked relative to the stack of first dies and carried by a package substrate. The semiconductor die assembly further includes a thermal spacer disposed between the package substrate and the thermally conductive casing. The thermal spacer can include a semiconductor substrate and plurality of conductive vias extending through the semiconductor substrate and electrically coupled to the stack of first semiconductor dies, the second semiconductor die, and the package substrate.

Abstract translation: 本文公开了具有热隔离件和相关联的系统和方法的堆叠的半导体管芯组件。 在一个实施例中，半导体管芯组件可以包括限定空腔的导热壳体，腔内的第一半导体管芯的堆叠，以及相对于第一管芯堆叠堆叠并由封装衬底承载的第二半导体管芯。 半导体管芯组件还包括设置在封装衬底和导热壳体之间的热隔离件。 热隔离物可以包括半导体衬底和延伸穿过半导体衬底并且电耦合到第一半导体管芯，第二半导体管芯和封装衬底的堆叠的多个导电通孔。

公开(公告)号：US20150279431A1

公开(公告)日：2015-10-01

申请号：US14242485

申请日：2014-04-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jian Li ,  Steven K. Groothuis

IPC: G11C5/02 ,  H01L25/18 ,  G11C7/12 ,  G11C5/06 ,  G11C7/10 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  G11C7/04 ,  G11C2207/107 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1319 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1659 ,  H01L2924/16747 ,  H01L2924/16787 ,  H01L2924/01047

Abstract: Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies.

Abstract translation: 本文公开了具有堆叠在分区逻辑管芯之间的存储器管芯和相关联的系统和方法的堆叠的半导体管芯组件。 在一个实施例中，半导体管芯组件可以包括第一逻辑管芯，第二逻辑管芯和限定外壳的导热壳体。 存储器管芯的堆叠可以设置在外壳内并且在第一和第二逻辑管芯之间。

公开(公告)号：US08921823B2

公开(公告)日：2014-12-30

申请号：US14243710

申请日：2014-04-02

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Jian Li

IPC: H01L45/00 ,  H01L21/06

CPC classification number: H01L45/1608 ,  H01L21/06 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/128 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1666 ,  H01L45/1675

Abstract: Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals.

公开(公告)号：US08766320B2

公开(公告)日：2014-07-01

申请号：US13872762

申请日：2013-04-29

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Jian Li ,  Chandra Mouli

IPC: H01L29/66

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/7926

Abstract: Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

Abstract translation: 示出了包括主体区域和由具有比身体区域更低带隙的半导体形成的连接区域的存储器件。 连接区域配置可以在擦除操作期间提供增加的栅极引起的漏极泄漏。 所显示的配置可以提供用于存储器操作的身体区域的可靠偏置，例如在升压操作期间擦除和容纳身体区域中的电荷。